參數(shù)資料
型號(hào)： 82803AAMRH-R
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 34/52頁(yè)
文件大?。?/td> 322K
代理商： 82803AAMRH-R
82803AA MRH-R
R
Datasheet
34
4.1.3.4.
Levelization
Levelization equalizes all RDRAM device read delays to the furthest device’s delay as seen by the MCH.
This allows RDRAM timings to remain consistent for each device as seen by the MCH.
4.1.3.5.
Initialization
The following steps are performed to initialize the MRH-R based memory subsystem after reset.
1. Assign unique serial addresses to all MRH-Rs.
2. Read all read-only registers and process the information.
3. Update the necessary read-write registers.
4. Initialize the MRH-R ‘expansion’ RAC via a CMOS broadcast command, enable the external
DRCG clock generators for ALL the ‘stick’ channels. Repeat for all MRH-Rs in the memory
subsystem.
5. Assign unique device IDs to each RDRAM and channel IDs to each MRH-R.
6. Repeat steps 1 to 3 for all levels of MRH-R and for all RDRAM channels.
7. Disable and powerdown the DRCGs and ‘stick’ RACs whose channels have no RDRAM devices
attached.
8. Wait for 5 ms from step 4 for the ‘stick’ channel clocks to stabilize and lock to the ‘expansion’
channel clocks. Note that steps 5-7 can proceed while waiting for this timeout.
9. Initialize the ‘stick’ channel RACs of ALL MRH-Rs (can be done using a CMOS Broadcast
command). Any ‘stick’ channel RACs that were powered down in step 7 will remain in that state
and will not be initialized.
10. Perform the levelization sequence.
4.1.3.6.
MRH-R Register Operations
This section describes the serial read and write operations for control registers within the MRH-R.
Figure 9 shows the control register read operation and Figure 10 shows the control register write
operation.
Figure 9. MRH-R Register Read
ExSCK
ExCmd
ExSIO
0
3
2
1
4
20
SRD
SRA
SINT
SD
36
52
68
reg_rd
Figure 10. MRH-R Register Write
reg_wr
ExSCK
ExCmd
ExSIO
0
3
2
1
4
20
SWR
SRA
SD
SINT
36
52
68
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