- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366259 > 80C03 Digital Temperature Sensor with SPI™ Interface, -55C to +125C, 8-MSOP, T/R PDF資料下載
參數(shù)資料
| 型號(hào)： | 80C03 |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | Digital Temperature Sensor with SPI™ Interface, -55C to +125C, 8-MSOP, T/R |
| 中文描述： | 80C03 AutoDUPLEX的CMOS以太網(wǎng)數(shù)據(jù)鏈路控制器手冊9 / 96 |
| 文件頁數(shù)： | 8/19頁 |
| 文件大?。?/td> | 247K |
| 代理商： | 80C03 |
80C03
4-8
MD400121/C
Match
Mode
1
0
0
1
Match
Mode
0
0
1
0
Function
Receiver Disable
Receive All Frames
Receive Station or Broadcast
Frames
Receive Station,
Broadcast/Multicast Frames
0
1
2
3
1
1
Match Mode Definition
Changing the receive Match Mode bits during frame re-
ception may change chip operation and give unpredictable
results.
Interrupt Enable and Frames-of-Interest
Bits 0-5 when set specify interrupt generation on occur-
rence of the corresponding frame reception condition.
They also specify the corresponding types of frames to be
Frames-of-Interest for use by the Receive Status Register
to control status loading.
Receive Status Register
The Receive Status Register is normally loaded with the
status of each received frame when the frame has been
received or rame reception has been erminated due o an
error condition. In addition, this register contains the Old/
New Status bit which is set when the Receive Status
Register s read or the chip s reset, and cleared only when
status is loaded for a Frame-of-Interest (as defined by bits
0-5 of the Receive Command Register). All other bits are
cleared upon chip reset.
Received Frame with Overflow Error
Received Frame with CRC Error
Received Frame with Dribble Error
Received Short Frame
Received End of Frame
Received Good Frame
7
6
5
3
2 1
4
0
BIT
Old/New Status
x
Receive Status Register Format
The Old/New Status bit write-protects the Receive Status
Register while it contains unread status for a Frame-of-
Interest. When this bit is zero, the register is write-
protected. The Old/New Status bit s cleared whenever he
status of a new Frame-of-Interest is loaded into the Re-
ceive Status Register and is set after that status is read.
When zero, it indicates “new status for a Frame-of-
Interest”.
Thus the status of any frame received following the recep-
tion of a Frame-of-Interest will not be loaded into the
Receive Status Register unless the previous status has
been read. If any following frame is received before the
status of the previous Frame-of-Interest has been read,
the new status will not be loaded, the Receive Discard
(RxDC) signal will be issued and the Receive FIFO will be
cleared.
With this one exception caused by a write-protect condi-
tion, the status of each frame is always loaded into the
Receive Status Register on completion of reception.
Any frame received will cause an nterrupt to be generated
if the corresponding Interrupt Enable bit is set. This
interrupt is reset upon reading the Receive Status Regis-
ter.
These conditions ensure that a maximum number of good
frames are received and retained.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 80C03 | AutoDUPLEX CMOS Ethernet Data Link Controller(AutoDUPLEX CMOS 以太網(wǎng)數(shù)據(jù)鏈路控制器) |
| 80C154S | Digital Temperature Sensor with SPI™ Interface, -55C to +125C, 8-DFN, T/R |
| 83C154S | CMOS 8-bit Microcontroller(258.00 k) |
| 81400000 | LACING CORD 25M RL |
| 81451 | BECHERKLEMME T2123 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 80C07B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:OPTICAL SAMPLING MODULES |
| 80C08C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:OPTICAL SAMPLING MODULES |
| 80C151SB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:HIGH-PERFORMANCE CHMOS MICROCONTROLLER |
| 80C152 | 制造商:Intel 功能描述: |
| 80C152JA | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。