- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366259 > 80C03 Digital Temperature Sensor with SPI™ Interface, -55C to +125C, 8-MSOP, T/R PDF資料下載
參數(shù)資料
| 型號(hào)： | 80C03 |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | Digital Temperature Sensor with SPI™ Interface, -55C to +125C, 8-MSOP, T/R |
| 中文描述： | 80C03 AutoDUPLEX的CMOS以太網(wǎng)數(shù)據(jù)鏈路控制器手冊(cè)9 / 96 |
| 文件頁(yè)數(shù)： | 6/19頁(yè) |
| 文件大?。?/td> | 247K |
| 代理商： | 80C03 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)當(dāng)前第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)
80C03
4-6
MD400121/C
Broadcast Address:
The six incoming destination ad-
dress bytes must all be FF hex. If the EDLC chip is
programmed to accept broadcast or Multicast Addresses
the frame will be received.
If the incoming frame is addressed to the EDLC chip
specifically (Destination Address matches the contents of
the Station Address Register), or is of general or group
interest (Broadcast or Multicast Address), the EDLC chip
will pass the frame exclusive of Preamble and FCS to the
CPU buffer and indicate any error conditions at the end of
the frame. If, however, the address does not match, as
soon as the mismatch is recognized the EDLC chip will
terminate reception and issue an RxDC.
The EDLC chip may be programmed via the Match Mode
bits of the Receive Command Register to gnore all frames
(Disable Receiver), accept all frames (Promiscuous
mode), accept frames with the proper Station Address or
the Broadcast Address (Station/Broadcast), or accept all
frames with the proper Station Address, the Broadcast
Address, or all Multicast Addresses (Station/Broadcast/
Multicast).
Terminating Reception
Reception is terminated when either of the following con-
ditions occur:
Carrier Sense Inactive:
Indicates that traffic is no longer
present on the Ethernet cable.
Overflow:
The host node for some reason is not able to
empty the Receive FIFO as rapidly as it is filled, and an
error occurs as frame data s ost. On average the Receive
FIFO must be serviced every 800 ns o avoid his condition.
Frame Reception Conditions
Upon terminating reception, the EDLC chip will determine
the status of the received frame and conditionally load it
into the Receive Status Register. An interrupt will be
issued if the appropriate conditions as specified in the
Receive Command Register are present. The EDLC chip
may report the following conditions at the end of frame
reception:
Overflow:
The EDLC internal Receive FIFO overflows.
Dribble Error:
Carrier Sense did not go inactive on a
receive data byte boundary.
CRC Error:
The 32-bit CRC transmitted with the frame
does not match that calculated upon reception.
Short Frame:
A frame containing less than 64 bytes of
information was received (including FCS).
Good Frame:
A frame is received that does not have a
CRC error, Shortframe or Overflow Condition.
System Interface
The EDLC chip system nterface consists of wo ndepend-
ent busses and respective control signals. Data is read
and written over the Receive/Transmit Data Bus RxTxD
(0-7). These transfers are controlled by the TxRDY and
TxWR signals for transmitted data and RxRDY and RxRD
for received data. All Commands and Station Addresses
are written, and all status read over a separate Command/
Status Bus CdSt (0-7). These transfers are controlled by
the CS, RD, WR and A0-A2 signals. The EDLC chip’s
command and status registers may be accessed at any
time. However, it is recommended that writing to the
command register be done only during interframe gaps.
With the exception of the two Match Mode bits in the
Receive Command Register, all bits in both command
registers are interrupt enable bits. Changing the interrupt
enable bits during frame transmission does not affect the
frame integrity. Asynchronous error events, however,
e.g., overflow, underflow, etc., may cause chip operation
to vary, f their corresponding enable bits are being altered
at the same time.
Reading the status registers may also occur at any time
during transmission or reception.
Status Registers are read only registers. Command and
Station Address registers are write only registers. Access
to these registers is via the CPU interface: Control signals
CS, RD , WR , and the Command/Status Data Bus
CdSt (0-7).
Station Address Register
The Station Address Register is 6 bytes in length. The
contents may be written n any order, with bit “0” of byte “0”
corresponding to the first bit received in the data stream,
and indicating whether the address is physical or logical.
Bit 7 of station address byte 5 is compared to the last bit of
Register
Address
A2
A1
Register Description
Read
A0
Write
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
—
—
—
—
—
—
Station Addr 0
Station Addr 1
Station Addr 2
Station Addr 3
Station Addr 4
Station Addr 5
Rx Command
Tx Command
Rx Status
Tx Status
Internal Register Addressing (8003 mode)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 80C03 | AutoDUPLEX CMOS Ethernet Data Link Controller(AutoDUPLEX CMOS 以太網(wǎng)數(shù)據(jù)鏈路控制器) |
| 80C154S | Digital Temperature Sensor with SPI™ Interface, -55C to +125C, 8-DFN, T/R |
| 83C154S | CMOS 8-bit Microcontroller(258.00 k) |
| 81400000 | LACING CORD 25M RL |
| 81451 | BECHERKLEMME T2123 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 80C07B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:OPTICAL SAMPLING MODULES |
| 80C08C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:OPTICAL SAMPLING MODULES |
| 80C151SB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:HIGH-PERFORMANCE CHMOS MICROCONTROLLER |
| 80C152 | 制造商:Intel 功能描述: |
| 80C152JA | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。