參數(shù)資料
型號(hào)： 80C03
元件分類： 溫度/濕度傳感器
英文描述： Digital Temperature Sensor with SPI™ Interface, -55C to +125C, 8-MSOP, T/R
中文描述： 80C03 AutoDUPLEX的CMOS以太網(wǎng)數(shù)據(jù)鏈路控制器手冊(cè)9 / 96
文件頁(yè)數(shù)： 4/19頁(yè)
文件大小： 247K
代理商： 80C03
80C03
4-4
MD400121/C
FIFO via TxWR only when TxRDY is HIGH. Actual
transmission of the data onto the network will only occur if
the network has not been busy for the minimum defer time
(9.6
μ
s) and any Backoff time requirements have been
satisfied. When transmission begins, the EDLC chip
activates he ransmit enable (TxEN) ine concurrently with
the transmission of the first bit of the Preamble and keeps
it active for the duration of the transmission.
Collision
When concurrent transmissions from two or more Eth-
ernet nodes occur (collision), the EDLC chip halts the
transmission of the data bytes in the Transmit FIFO and
transmits a Jam pattern consisting of 55555555 hex. At
the end of the Jam transmission, the EDLC chip issues a
TxRET signal to the CPU and begins the Backoff wait
period.
To reinitiate transmission, the initial bytes of the frame
information fields must be reloaded into the EDLC Trans-
mit FIFO. The TxRET is used to indicate to the buffer
manager the need for frame reinitialization. The reloading
of the Transmit FIFO may be done prior to the Backoff
interval elapsing, so that no additional delay need be
incurred to retransmission.
Scheduling of retransmission is determined by a con-
trolled randomization process called Truncated Binary
Exponential Backoff. The EDLC chip waits a random
interval between 0 and 2
K
slot times (51.2
μ
s per slot time)
before attempting retransmission, where “K” s the current
transmission attempt number (not to exceed 10).
When 16 consecutive attempts have been made at trans-
mission and all have been terminated due to collision, the
EDLC Transmit Control sets an error status bit and issues
an interrupt to the CPU if enabled.
Terminating Transmission
Transmission Terminates under the following conditions:
Normal:
The frame has been transmitted successfully
without contention. Loading of the last data byte into the
Transmit FIFO is signaled to the EDLC chip by activation
of the RxTxEOF signal concurrently with the last byte of
data loaded into the Transmit FIFO. This line acts as a
ninth bit in the Transmit FIFO. When this last byte is
serialized, f he chip s not n Transmit No CRC mode, hen
the CRC is appended and transmitted concluding frame
transmission. The Transmission Successful bit of the
Transmit Status Register will be set by a normal termina-
tion.
Collision:
Transmission attempted by two or more Eth-
ernet nodes. The Jam sequence is transmitted, the Colli-
sion status bit s set, transmit Collision Counter s updated,
the TxRET signal is generated, and the Backoff interval
begun.
Underflow:
Transmit data is not ready when needed for
transmission. Once transmission has begun, the EDLC
chip on average requires one transmit byte every 800 ns
in order to avoid Transmit FIFO underflow (starvation). If
this condition occurs, the EDLC chip terminates the trans-
mission, issues a TxRET signal, and sets the Transmit-
Underflow status bit.
16 Transmission Attempts:
If a Collision occurs for the
sixteenth consecutive time, the 16-Transmission-At-
tempts status bit is set, the Collision status bit is set, the
TxRET signal is generated, and the Backoff interval be-
gun. The counter that keeps track of the number of
collisions s modulo 16 and therefore rolls over on the 17th
collision. Bits 15 to 11 on the Collision Count Registers
(80C03 mode) indicates the attempt counter used for
Collision back-off. These can be read and cleared as
described in the Transmit Command register description.
At the completion of every transmission or retransmission,
new status information is loaded into the Transmit Status
Register. Dependent upon the bits enabled in the Trans-
mit Command Register, an interrupt will be generated for
the just completed transmission. In both collision and
underflow the TxRET signal is activated.
Receiving
The EDLC chip is continuously monitoring the network.
When activity is recognized via the Carrier Sense (CSN)
line going active, the EDLC chip synchronizes itself to the
incoming data stream during the Preamble, and then
examines the destination address field of the frame. De-
pending on the Address Match Mode specified, the EDLC
chip will either recognize the frame as being addressed to
itself in a general or specific fashion or abort the frame
reception. The 80C03 also allows counting of all collisions
seen on the network.
Preamble Processing
The EDLC chip recognizes activity on the Ethernet via the
Carrier Sense line. The Preamble is normally 64 bits (8
bytes) long. The Preamble consists of a sequence of 62
alternating “1”s and “0”s followed by “11”, with the frame
information fields immediately following. In order for the
decoder phase-lock to occur, the EDLC chip waits 16 bit
times before ooking for the “11” end of preamble ndicator.
If the EDLC chip receives a “00” before receiving the “11”
in the Preamble, an error condition has occurred. The
frame is not received, and the EDLC chip begins monitor-
ing the network for a carrier again.
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