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參數(shù)資料
| 型號： | 80C03 |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | Digital Temperature Sensor with SPI™ Interface, -55C to +125C, 8-MSOP, T/R |
| 中文描述： | 80C03 AutoDUPLEX的CMOS以太網(wǎng)數(shù)據(jù)鏈路控制器手冊9 / 96 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 247K |
| 代理商： | 80C03 |
80C03
4-12
MD400121/C
RxDC does not activate on errors when the associated
Interrupt Enable bit is set. In this case, EOF will be
generated instead when the Receive FIFO is read out.
This allows reception of frames with errors. RxDC acts
internally to clear the Receive FIFO.
TxRDY Transmit Ready (Output):
Indicates that the
Transmit FIFO has space available for at least one data
byte. This signal will remain active high as ong as one byte
of space exists for transmitted data to be written into.
When this condition no longer exists, TxRDY will be
deasserted with respect to the leading edge of the TxWR
strobe that fills the Transmit FIFO. TxRDY is forced
inactive during Reset, and when TxRET is active. Active
HIGH. Goes high after Reset.
TxWR Transmit Write (Input):
Synchronizes data trans-
fer from the RxTxD Bus to the Transmit FIFO. Data is
written to the FIFO on the rising edge of this signal. This
signal should not be active unless TxRDY is high. Active
LOW.
TxRet Transmit Retransmit (Output):
Asserted when-
ever either transmit underflow or transmit collision condi-
tions occur. It is nominally 800 ns in width. Active HIGH.
Asserted by Reset. TxRET clears the internal Transmit
FIFO.
ADUPLX* - Input (PLCC Package Only):
Active low
input used to set 80C03 in AutoDUPLEX Mode. In this
mode the transmitter will not defer to active carrier sense
signal.
Command/Status Interface
CdSt (0-7) Command/Status Data Bus (I/O):
These ines
carry commands and status as well as station address
initialization nformation between he EDLC chip and CPU.
These lines are nominally high impedance until activated
by CS and RD being simultaneously active.
A0-A2 Address (0-2) (Input):
Address lines to select the
proper EDLC internal registers for reading or writing.
CS Chip Select (Input):
Chip Select nput, must be active
in conjunction with RD or WR to successfully access the
EDLC internal registers. Active LOW.
RD Read (Input):
Enables reading of the EDLC internal
registers in conjunction with CS. Data from the internal
registers is enabled via the falling edge of RD and is valid
on the rising edge of the signal. Active LOW.
WR Write (Input):
Enables writing of the EDLC internal
registers in conjunction with CS. Write data on the Cdst
(0-7) data lines must be set up relative to the rising edge
of the signal. Active LOW.
INT Interrupt (Output):
Enabled as outlined above by a
variety of transmit and receive conditions. Remains active
until the status register containing the reason for the
interrupt is read. Active HIGH.
RESET (Input):
Initializes control logic, clears command
registers, clears the Transmit Status Register, clears bits
0-5 of the Receive Status Register, sets the Old/New
Status bit (bit 7 of the Receive Status Register), asserts
RxDC and TxRET and clears the Receive and Transmit
FIFOs. In addition, TxRDY is forced low during a reset.
TxRDY goes high when RESET goes high, indicating the
EDLC chip is ready to transmit. RESET is active LOW.
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