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參數(shù)資料
| 型號： | 7C187-15 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64K x 1 Static RAM |
| 中文描述： | 64K的× 1靜態(tài)RAM |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 142K |
| 代理商： | 7C187-15 |
CY7C187
Document #: 38-05044 Rev. **
Page 3 of 9
AC Test Loads and Waveforms
(R1 255
MIL)
(R1 255
MIL)
(480
MIL)
(480
MIL)
3.0V
5V
OUTPUT
R1 329
R2 202
30 pF
GND
90%
90%
10%
≤
5 ns
≤
5 ns
5V
OUTPUT
C187
–
4
R2 202
5 pF
C187
–
5
(a)
(b)
OUTPUT
1.73V
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
R1 329
Equivalent to:
TH
é
VENIN EQUIVALENT
10%
OUTPUT
1.90V
Military
Commercial
ALL INPUT PULSES
167
125
Switching Characteristics
Over the Operating Range
[6]
7C187-15
Min.
7C187-20
Min.
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
[9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Notes:
6.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 30-pF load capacitance.
7.
At any given temperature and voltage condition, t
is less than t
for any given device.
8.
t
and t
are specified with C
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
9.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Description
Max.
Max.
Unit
Read Cycle Time
Address to Data Valid
Output Hold from Address Change
CE LOW to Data Valid
CE LOW to Low Z
[7]
CE HIGH to High Z
[7, 8]
CE LOW to Power Up
CE HIGH to Power Down
15
20
ns
ns
ns
ns
ns
ns
ns
ns
15
20
3
5
15
20
3
5
8
8
0
0
15
20
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
[8]
15
12
12
0
0
12
10
0
5
20
15
15
0
0
15
10
0
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 7C187-20 | 64K x 1 Static RAM |
| 7C187-25 | 16-Bit, Bidirectional Transceiver |
| 7C187-35 | 64K x 1 Static RAM |
| 7C192-12 | 64K x 4 Static RAM with Separate I/O |
| 7C192-15 | 64K x 4 Static RAM with Separate I/O |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 7C187-20 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:64K x 1 Static RAM |
| 7C187-25 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:64K x 1 Static RAM |
| 7C187-35 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:64K x 1 Static RAM |
| 7C187NT | 制造商:Cypress Semiconductor 功能描述: |
| 7C187NT WAF | 制造商:Cypress Semiconductor 功能描述: |
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