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參數(shù)資料
| 型號： | 7C185-35 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | IC 16-BIT BUFF/LINE DVR 48-SSOP |
| 中文描述： | 8K的× 8靜態(tài)RAM |
| 文件頁數(shù)： | 6/11頁 |
| 文件大小： | 197K |
| 代理商： | 7C185-35 |
CY7C185
Document #: 38-05043 Rev. *A
Page 6 of 11
Notes:
15. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
and t
.
16. If CE
1
goes HIGH or CE
2
goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
Switching Waveforms
(continued)
t
WC
t
AW
t
SA
t
HA
t
HD
t
SD
t
SCE1
WE
DATA I/O
ADDRESS
CE
1
DATA
IN
VALID
t
SCE2
CE
2
rite Cycle No. 2 (CE Controlled)
[13,14,15]
t
HD
t
SD
t
LZWE
t
SA
t
HA
t
AW
t
WC
t
HZWE
DATA
IN
VALID
t
SCE1
t
SCE2
CE
1
CE
2
ADDRESS
DATA I/O
WE
Write Cycle No. 3 (WE Controlled, OE LOW)
[13,14,15,16]
NOTE 14
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| 7C185NT | 制造商:Cypress Semiconductor 功能描述: |
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| 7C186C | 制造商:Cypress Semiconductor 功能描述: |
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