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參數(shù)資料
| 型號(hào)： | 7C185-35 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | IC 16-BIT BUFF/LINE DVR 48-SSOP |
| 中文描述： | 8K的× 8靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 4/11頁(yè) |
| 文件大?。?/td> | 197K |
| 代理商： | 7C185-35 |
CY7C185
Document #: 38-05043 Rev. *A
Page 4 of 11
Switching Characteristics
Over the Operating Range
[6]
7C185-15
Min.
7C185-20
Min.
7C185-25
Min.
7C185-35
Min.
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE1
t
ACE2
t
DOE
t
LZOE
t
HZOE
t
LZCE1
t
LZCE2
t
HZCE
Description
Max.
Max.
Max.
Max.
Unit
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW to Data Valid
CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[7]
CE
1
LOW to Low Z
[8]
CE
2
HIGH to Low Z
CE
1
HIGH to High Z
[7, 8]
CE
2
LOW to High Z
CE
1
LOW to Power-Up
CE
2
to HIGH to Power-Up
CE
1
HIGH to Power-Down
CE
2
LOW to Power-Down
15
20
25
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
20
25
35
3
5
5
5
15
15
8
20
20
9
25
25
12
35
35
15
3
3
3
3
7
8
10
10
3
3
5
3
5
3
5
3
7
8
10
10
t
PU
0
0
0
0
ns
t
PD
15
20
20
20
ns
Write Cycle
[9]
t
WC
t
SCE1
t
SCE2
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
6.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
7.
t
t
, and t
are specified with C
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady state voltage.
8.
At any given temperature and voltage condition, t
is less than t
LZCE1
and t
LZCE2
for any given device.
9.
The internal write time of the memory is defined by the overlap of CE
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Write Cycle Time
CE
1
LOW to Write End
CE
2
HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
[7]
WE HIGH to Low Z
15
12
12
12
0
0
12
8
0
20
15
15
15
0
0
15
10
0
25
20
20
20
0
0
15
10
0
35
20
20
25
0
0
20
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
7
7
8
3
5
5
5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 7C187-15 | 64K x 1 Static RAM |
| 7C187-20 | 64K x 1 Static RAM |
| 7C187-25 | 16-Bit, Bidirectional Transceiver |
| 7C187-35 | 64K x 1 Static RAM |
| 7C192-12 | 64K x 4 Static RAM with Separate I/O |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 7C185-35VCT | 制造商:undefined 功能描述: |
| 7C185B 7C186B WAF | 制造商:Cypress Semiconductor 功能描述: |
| 7C185NT | 制造商:Cypress Semiconductor 功能描述: |
| 7C185NVI | 制造商:Cypress Semiconductor 功能描述: |
| 7C186C | 制造商:Cypress Semiconductor 功能描述: |
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