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參數(shù)資料
| 型號： | 7C1359A-166 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256K x 18 Synchronous-Pipelined Cache Tag RAM |
| 中文描述： | 256 × 18的同步高速緩存標(biāo)記內(nèi)存流水線 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 244K |
| 代理商： | 7C1359A-166 |
CY7C1359A/GVT71256T18
Document #: 38-05120 Rev. **
Page 11 of 24
TAP AC Switching Characteristics
Over the Operating Range
[18, 19]
Parameter
Clock
t
THTH
f
TF
t
THTL
t
TLTH
Output Times
t
TLQX
t
TLQV
t
DVTH
t
THDX
Set-up Times
t
MVTH
t
CS
Hold Times
t
THMX
t
CH
Notes:
18. t
and t
refer to the set-up and hold time requirements of latching data from the boundary scan register.
19. Test conditions are specified using the load in TAP AC Test Conditions.
Description
Min.
Max
Unit
Clock Cycle Time
Clock Frequency
Clock HIGH Time
Clock LOW Time
20
ns
MHz
ns
ns
50
8
8
TCK LOW to TDO Unknown
TCK LOW to TDO Valid
TDI Valid to TCK HIGH
TCK HIGH to TDI Invalid
0
ns
ns
ns
ns
10
5
5
TMS Set-up
Capture Set-up
5
5
ns
ns
TMS Hold
Capture Hold
5
5
ns
ns
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