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參數(shù)資料
| 型號： | 7C1359A-166 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256K x 18 Synchronous-Pipelined Cache Tag RAM |
| 中文描述： | 256 × 18的同步高速緩存標記內(nèi)存流水線 |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 244K |
| 代理商： | 7C1359A-166 |
CY7C1359A/GVT71256T18
Document #: 38-05120 Rev. **
Page 10 of 24
Figure 2. TAP Controller Block Diagram
0
0
1
2
.
.
29
30
31
Boundary Scan Register
Identification Register
0
1
2
.
.
.
.
x
0
1
2
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TDI
TDI
[14]
TAP DC Electrical Characteristics
(20
°
C < T
j
< 110
°
C; V
CC
= 3.3V
–
0.2V and +0.3V unless otherwise noted)
Parameter
V
IH
V
Il
IL
I
IL
O
Description
Test Conditions
Min.
2.0
–
0.3
–
5.0
–
5.0
Max.
V
CC
+ 0.3
0.8
5.0
5.0
Unit
V
V
μ
A
μ
A
Input High (Logic 1) Voltage
[15, 16]
Input Low (Logic 0) Voltage
[15, 16]
Input Leakage Current
Output Leakage Current
0V < V
IN
< V
CC
Output disabled,
0V < V
IN
< V
CCQ
I
OLC
= 100
μ
A
I
OHC
= 100
μ
A
I
OLT
= 8.0 mA
I
OHT
= 8.0 mA
V
OLC
V
OHC
V
OLT
V
OHT
Notes:
14. X = 53 for this device.
15. All Voltage referenced to V
(GND).
16. Overshoot: V
(AC)<V
+
1.5V for t<t
/2, Undershoot: V
(AC)<
–
0.5V for t<t
/2, Power-up: V
<3.6V and V
<3.135V and V
<1.4V for t<200 ms.
During normal operation, V
CCQ
must not exceed V
CC
. Control input signals (such as GW, ADSC, etc.) may not have pulse widths less than t
KHKL
(min.).
17. This parameter is sampled.
LVCMOS Output Low Voltage
[15, 17]
LVCMOS Output High Voltage
[15, 17]
LVTTL Output Low Voltage
[15]
LVTTL Output High Voltage
[15]
0.2
V
V
V
V
V
CC
–
0.2
0.4
2.4
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