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參數(shù)資料
| 型號(hào)： | 7C1351-66 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 128Kx36 Flow-Through SRAM with NoBL TM Architecture |
| 中文描述： | 128K × 36至流通過(guò)與總線延遲TM架構(gòu)的SRAM |
| 文件頁(yè)數(shù)： | 5/13頁(yè) |
| 文件大小： | 195K |
| 代理商： | 7C1351-66 |
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CY7C1351
5
.
Cycle Description Truth Table
[1, 2, 3, 4, 5, 6]
Operation
Address
used
CE
CEN
ADV/
LD
WE
BWS
x
CLK
Comments
Deselected
External
1
0
L
X
X
L-H
I/Os three-state following next
recognized clock.
Suspend
-
X
1
X
X
X
L-H
Clock ignored, all operations
suspended.
Begin Read
External
0
0
0
1
X
L-H
Address latched.
Begin Write
External
0
0
0
0
Valid
L-H
Address latched, data presented
two valid clocks later.
Burst Read
Operation
Internal
X
0
1
X
X
L-H
Burst Read operation. Previous
access was a Read operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE.
Burst Write
Operation
Internal
X
0
1
X
Valid
L-H
Burst Write operation. Previous
access was a Write operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE. Bytes written are deter-
mined by BWS
[3:0]
.
Notes:
1.
X=
”
Don't Care
”
, 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWS
= 0 signifies at least one Byte Write Select is active, BWS
x
= Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
Write is defined by WE and BWS
. See Write Cycle Description table for details.
The DQ and DP pins are controlled by the current cycle and the OE signal.
CEN=1 inserts wait states.
Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
OE assumed LOW.
2.
3.
4.
5.
6.
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