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參數(shù)資料
| 型號： | 7C1351-66 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 128Kx36 Flow-Through SRAM with NoBL TM Architecture |
| 中文描述： | 128K × 36至流通過與總線延遲TM架構(gòu)的SRAM |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 195K |
| 代理商： | 7C1351-66 |
CY7C1351
10
Switching Waveforms
CEN
CLK
ADDRESS
CE
WE
Data-
In/Out
t
CYC
t
CH
t
CL
t
CENS
t
CENH
RA1
t
AH
t
AS
t
WS
t
WH
t
CES
t
CEH
t
CDV
Q4
Out
Q1
Out
= DON
’
T CARE
= UNDEFINED
WE is the combination of WE & BWS
x
to define a write cycle (see Write Cycle Description table).
CE is the combination of CE
1
, CE
2
, and CE
3
. All chip selects need to be active in order to select
the device. Any chip select can deselect the device. RAx stands for Read Address X, WAx stands for
Write Address X, Dx stands for Data-in X, Qx stands for Data-out X.
D2
In
D5
In
R
W
D
W
R
R
R
S
R
D
D
WA2
RA3
RA4
WA5
RA6
RA7
t
CLZ
t
DOH
Q3
Out
t
CHZ
Device
originally
deselected
Q7
Out
t
CHZ
t
CENS
t
CENH
t
DOH
Q6
Out
Read/Write/Deselect Sequence
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|---|---|
| 7C1351G-117AZC | 制造商:Cypress Semiconductor 功能描述: |
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| 7C1351GC | 制造商:Cypress Semiconductor 功能描述: |
| 7C1351XC | 制造商:Cypress Semiconductor 功能描述: |
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