2006 Teridian Semiconductor Corporation Rev. 2" />
參數(shù)資料
型號: 78P2352-DB/CMI
廠商: Maxim Integrated Products
文件頁數(shù): 9/42頁
文件大小: 0K
描述: BOARD DEMO 78P2352 COAX CABLE
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
系列: *
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
Page: 17 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
PIN DESCRIPTION (CONTINUED)
RECEIVER PINS
NAME
PIN
TYPE
DESCRIPTION
POx0D
POx1D
POx2D
POx3D
46, 51
45, 52
42, 55
41, 56
CO
Receive (Parallel Mode) Data Output:
Recovered receive data deserialized into four-bit CMOS parallel (nibble)
outputs. The MSB (POx3D) is received first. Active, but undefined during
reset.
Note: During Loss of Signal conditions, data outputs are held low.
POxCK
38, 59
CO
Receive (Parallel Mode) Clock Output:
A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock output generated by
dividing down the recovered receive clock. By default, receive data is
clocked out on the falling edge. Active during reset.
Note: During Loss of Signal conditions, the clock will remain on the last
divided down phase selection of the Rx DLL and output a steady clock.
SOxDP
SOxDN
28, 69
29, 68
PO
Receive (Serial Mode) Data Output:
Recovered receive serial NRZ data at LVPECL levels. Active, but undefined
during reset.
Note: During Loss of Signal conditions, data outputs are held at logic 0.
SOxCKP
SOxCKN
25, 72
26, 71
PO
Receive (Serial Mode) Clock Output:
Recovered receive serial clock. By default, recovered serial NRZ data is
clocked out the falling edge of SOxCKP. Active during reset.
Note: During Loss of Signal conditions, the clock will remain on the last
phase selection of the Rx DLL and output a steady clock.
RXxP
RXxN
118, 107
119, 106
A/
PI
Receiver CMI or LVPECL Input:
The input is either transformer-coupled to coaxial cable for CMI data or AC-
coupled at LVPECL levels to an optical transceiver module for NRZ data.
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