2006 Teridian Semiconductor Corporation Rev. 2" />
參數(shù)資料
型號: 78P2352-DB/CMI
廠商: Maxim Integrated Products
文件頁數(shù): 2/42頁
文件大小: 0K
描述: BOARD DEMO 78P2352 COAX CABLE
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
系列: *
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
Page: 10 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
REGISTER DESCRIPTION (CONTINUED)
LEGEND
TYPE
DESCRIPTION
TYPE
DESCRIPTION
R/O
Read only
R/W
Read or Write
R/C
Read and Clear
GLOBAL REGISTERS
ADDRESS 0-0: MASTER CONTROL REGISTER
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
7
E4
R/W
0
Line Rate Selection:
Selects the line rate of all channels as well as the input clock frequency
at the CKREFP/N pins.
0: OC-3, STS-3, STM-1 (155.52MHz)
1: E4 (139.264MHz)
6
--
R/W
0
Unused
5
PAR
R/W
0
Serial/Parallel Interface Selection:
Selects the interface to the framer.
0: Serial LVPECL
1: 4-bit Parallel CMOS
4:3
CKSL
[1:0]
R/W
XX
Reference Clock Frequency Selection:
Selects the reference clock frequency input at CKREFP/N pins.
11: 155.52MHz / 139.264MHz (differential LVPECL)
10: 77.76MHz / NA (single-ended CMOS)
00: 19.44MHz / 17.408MHz (single-ended CMOS)
Secondary values correspond to E4 frequencies. Default values depend
on the CKSL pin selection upon reset.
2:1
--
R/W
X0
Reserved.
0
SRST
R/W
0
Register Soft-Reset:
When this bit is set, all registers are reset to their default values. This
register bit is self-clearing.
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