2006 Teridian Semiconductor Corporation Rev. 2" />
參數(shù)資料
型號(hào)： 78P2352-DB/CMI
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 8/42頁(yè)
文件大?。?/td> 0K
描述： BOARD DEMO 78P2352 COAX CABLE
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
系列： *
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
Page: 16 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
PIN DESCRIPTION
LEGEND
TYPE
DESCRIPTION
TYPE
DESCRIPTION
A
Analog Pin
(Tie unused pins to ground)
PO
LVPECL-Compatible Differential Output
(Tie unused pins to supply or leave floating)
CIT
3-State CMOS Digital Input
CO
CMOS Digital Output
(Leave unused pins floating)
CI
CMOS Digital Input
(Tie unused pins to ground)
COZ
CMOS Tristate Digital Output
(Leave unused pins floating)
CIU
CMOS Digital Input w/ Pull-up
OD
Open-drain Digital Output
(Leave unused pins floating)
CID
CMOS Digital Input w/ Pull-down
S
Supply
CIS
CMOS Schmitt Trigger Input
(Tie unused pins to ground)
G
Ground
PI
LVPECL-Compatible Differential Input
(Tie unused pins to ground)
TRANSMITTER PINS
NAME
PIN
TYPE
DESCRIPTION
PIx0D
PIx1D
PIx2D
PIx3D
31, 66
32, 65
33, 64
34, 63
CI
Transmit (Parallel Mode) Data Input:
Four-bit CMOS parallel (nibble) inputs. Data is latched in on the rising edge
(default) of the transmit parallel clock and serialized with the MSB (PIx3D)
transmitted first.
PIxCK
30, 67
CIS
Transmit (Parallel Mode) Clock Input:
A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock input that must be
source synchronous with the reference clock supplied at the CKREFP/N pins.
Used only in Slave Parallel Mode and Loop-timing Parallel Mode.
PTOxCK
35, 62
CO
Transmit (Parallel Mode) Clock Output:
A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock output that is
intended to latch in synchronous parallel data. Active during reset. Used only
in Master Parallel Mode (output disabled in all other transmit modes).
SIxDP
SIxDN
10, 87
11, 86
PI
Transmit (Serial Mode) Data Input:
Differential NRZ data input. See Transmitter Operation section for more info
on different clocking/timing modes.
SIxCKP
SIxCKN
7, 90
8, 89
PI
Transmit (Serial Mode) Clock Input:
A 155.52MHz synchronous differential input clock used to clock in the serial
NRZ data. By default, data is clocked in on the rising edge of SIxCKP.
CMIxP
CMIxN
121, 104
122, 103
A
Transmit (Serial Mode) CMI Data Output:
A CMI encoded data signal conforming to the relevant ITU-T G.703 pulse
templates when properly terminated and transformer coupled to 75 cable.
Outputs are tri-stated when transmitter is disabled. Active, but undefined
during reset.
TXxCKP
TXxCKN
124, 101
125, 100
PO
Transmit (Serial Mode) Clock Output:
A 2x line rate LVPECL clock output used to clock out the transmit CMI data.
Used for diagnostics or far end re-timing. Active during reset.
ECLxP
ECLxN
127, 98
128, 97
PO
Transmit (Serial Mode) LVPECL Data Output:
Transmit NRZ data outputs used for interfacing with optical transceiver
modules when in Fiber (NRZ) mode.
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78P2352-IGT 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Dual Channel OC-3/ STM1-E/ E4 LIU
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