
Rev.1.02 2003.06.25 page 49 of 53
7544 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
A-D Converter Characteristics
Table 14 A-D Converter characteristics (V
CC
= 4.0 to 5.5 V, V
SS
= 0 V, Ta =
–
20 to 85
°
C, unless otherwise noted)
Resolution
Absolute accuracy
(quantification error excluded)
Conversion time
Ladder resistor
Reference power source
input current
A-D port input current
Min.
Typ.
Max.
8
±3
Symbol
Parameter
Limits
Unit
Test conditions
V
REF
= 5.0 V
V
REF
= 3.0 V
Bits
LSB
tc(X
IN
)
k
μA
μA
109
200
120
5.0
—
ABS
t
CONV
R
LADDER
I
VREF
I
I(AD)
37
135
80
50
30
Timing Requirements
Table 15 Timing requirements (V
CC
= 4.0 to 5.5 V, V
SS
= 0 V, Ta =
–
20 to 85
°
C, unless otherwise noted)
Min.
2
125
50
50
200
80
80
2000
800
800
800
370
370
220
100
Typ.
Max.
Symbol
______
t
W
(RESET)
t
C
(X
IN
)
t
WH
(X
IN
)
t
WL
(X
IN
)
t
C
(CNTR
0
)
t
WH
(CNTR
0
)
t
WL
(CNTR
0
)
t
C
(CNTR
1
)
t
WH
(CNTR
1
)
t
WL
(CNTR
1
)
t
C
(S
CLK
)
t
WH
(S
CLK
)
t
WL
(S
CLK
)
t
su
(RxD
–
S
CLK
)
t
h
(S
CLK
–
RxD)
Parameter
Limits
Unit
Reset input
“
L
”
pulse width
External clock input cycle time
External clock input
“
H
”
pulse width
External clock input
“
L
”
pulse width
CNTR
0
input cycle time
CNTR
0
, INT
0
, INT
1
, input
“
H
”
pulse width
CNTR
0
, INT
0
, INT
1
, input
“
L
”
pulse width
CNTR
1
input cycle time
CNTR
1
input
“
H
”
pulse width
CNTR
1
input
“
L
”
pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input
“
H
”
pulse width (Note)
Serial I/O clock input
“
L
”
pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
In this time, bit 6 of the serial I/O control register (address 001A
16
) is set to
“
1
”
(clock synchronous serial I/O is selected).
When bit 6 of the serial I/O control register is
“
0
”
(clock asynchronous serial I/O is selected), the rating values are divided by 4.