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參數(shù)資料
| 型號(hào)： | 7544 |
| 英文描述： | 3.3V LDO POSITVE VOLTAGE REGULATOR 2% TOL. |
| 中文描述： | 7544Group數(shù)據(jù)表數(shù)據(jù)表503K/JUN.25.03 |
| 文件頁數(shù)： | 31/54頁 |
| 文件大?。?/td> | 503K |
| 代理商： | 7544 |
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Rev.1.02 2003.06.25 page 31 of 53
7544 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Reset Circuit
The microcomputer is put into a reset status by holding the RE-
SET pin at the
“
L
”
level for 2
μ
s or more when the power source
voltage is 4.5 to 5.5 V and X
IN
is in stable oscillation.
After that, this reset status is released by returning the RESET pin
to the
“
H
”
level. The program starts from the address having the
contents of address FFFD
16
as high-order address and the con-
tents of address FFFC
16
as low-order address.
In the case of f(
φ
)
≤
8 MHz, the reset input voltage must be 0.9 V
or less when the power source voltage passes 4.5 V.
______
Fig. 35 Example of reset circuit
Fig. 36 Timing diagram at reset
(Note)
0.2 V
CC
0 V
0 V
Poweron
V
CC
RESET
V
CC
RESET
Power source
voltage
detection circuit
Power source
voltage
Reset input
voltage
Note :
Reset release voltage Vcc 4.5V
Data
Address
8-13 clock cycles
Reset address from the
vector table
1 :
A built-in ring oscillator applies about RING
2 MHz,
φ
250 kHz frequency clock
at average of Vcc = 5 V.
2 :
The mark
“
”
means that the address is changeable depending on the previous state.
3 :
These are all internal signals except RESET.
Notes
FFFC
FFFD
AD
H
,AD
L
AD
L
AD
H
Clock from built-in
ring oscillator RING
φ
RESET
RESET
OUT
SYNC
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