參數(shù)資料
型號： 7544
英文描述： 3.3V LDO POSITVE VOLTAGE REGULATOR 2% TOL.
中文描述： 7544Group數(shù)據(jù)表數(shù)據(jù)表503K/JUN.25.03
文件頁數(shù)： 30/54頁
文件大?。?/td> 503K
代理商： 7544
Rev.1.02 2003.06.25 page 30 of 53
7544 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Watchdog Timer
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a runaway.
The watchdog timer consists of an 8-bit watchdog timer H and an
8-bit watchdog timer L, being a 16-bit counter.
Standard operation of watchdog timer
The watchdog timer stops when the watchdog timer control regis-
ter (address 0039
16
) is not set after reset. Writing an optional
value to the watchdog timer control register (address 0039
16
)
causes the watchdog timer to start to count down. When the
watchdog timer H underflows, an internal reset occurs. Accord-
ingly, it is programmed that the watchdog timer control register
(address 0039
16
) can be set before an underflow occurs.
When the watchdog timer control register (address 0039
16
) is
read, the values of the high-order 6-bit of the watchdog timer H,
STP instruction disable bit and watchdog timer H count source se-
lection bit are read.
Initial value of watchdog timer
By a reset or writing to the watchdog timer control register (ad-
dress 0039
16
), the watchdog timer H is set to
“
FF
16
”
and the
watchdog timer L is set to
“
FF
16
”
.
Operation of watchdog timer H count source selection bit
A watchdog timer H count source can be selected by bit 7 of the
watchdog timer control register (address 0039
16
). When this bit is
“
0
”
, the count source becomes a watchdog timer L underflow sig-
nal. The detection time is 131.072 ms at f(X
IN
)=8 MHz.
When this bit is
“
1
”
, the count source becomes f(X
IN
)/16. In this
case, the detection time is 512
μ
s at f(X
IN
)=8 MHz.
This bit is cleared to
“
0
”
after reset.
Operation of STP instruction disable bit
When the watchdog timer is in operation, the STP instruction can
be disabled by bit 6 of the watchdog timer control register (ad-
dress 0039
16
).
When this bit is
“
0
”
, the STP instruction is enabled.
When this bit is
“
1
”
, the STP instruction is disabled, and an inter-
nal reset occurs if the STP instruction is executed.
Once this bit is set to
“
1
”
, it cannot be changed to
“
0
”
by program.
This bit is cleared to
“
0
”
after reset.
Fig. 33 Block diagram of watchdog timer
Fig. 34 Structure of watchdog timer control register
X
IN
Data bus
“
0
”
“
1
”
Watchdog timer H count
source selection bit
1/16
Reset
circuit
STP Instruction disable bit
STP Instruction
Watchdog timer H (8)
Write "FF
16
" to the
watchdog timer
control register
Internal
reset
RESET
Watchdog timer L (8)
Write
“
FF
16
”
to the
watchdog timer
control register
Watchdog timer control register
(WDTCON: address 0039
16
, initial value: 3F
16
)
Watchdog timer H (read only for high-order 6-bit)
STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count source selection bit
0 : Watchdog timer L underflow
1 : f(X
IN
)/16
b7 b0
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