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參數(shù)資料
| 型號： | 7544 |
| 英文描述： | 3.3V LDO POSITVE VOLTAGE REGULATOR 2% TOL. |
| 中文描述： | 7544Group數(shù)據(jù)表數(shù)據(jù)表503K/JUN.25.03 |
| 文件頁數(shù)： | 13/54頁 |
| 文件大?。?/td> | 503K |
| 代理商： | 7544 |
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Rev.1.02 2003.06.25 page 13 of 53
7544 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
I/O Ports
[Direction registers] PiD
The I/O ports have direction registers which determine the input/
output direction of each pin. Each bit in a direction register corre-
sponds to one pin, and each pin can be set to be input or output.
When
“
1
”
is set to the bit corresponding to a pin, this pin becomes
an output port. When
“
0
”
is set to the bit, the pin becomes an in-
put port.
When data is read from a pin set to output, not the value of the pin
itself but the value of port latch is read. Pins set to input are float-
ing, and permit reading pin values.
If a pin set to input is written to, only the port latch is written to and
the pin remains floating.
[Pull-up control register] PULL
By setting the pull-up control register (address 0016
16
), ports P0
and P3 can exert pull-up control by program. However, pins set to
output are disconnected from this control and cannot exert pull-up
control.
[Port P1P3 control register] P1P3C
By setting the port P1P3 control register (address 0017
16
), a
CMOS input level or a TTL input level can be selected for ports
P1
0
, P1
2
, P3
4
, and P3
7
by program.
Fig. 14 Structure of port P1P3 control register
Fig. 13 Structure of pull-up control register
Pull-up control register
(PULL: address 0016
16
, initial value: 00
16
)
P0
0
pull-up control bit
P0
1
pull-up control bit
P0
2
, P0
3
pull-up control bit
P0
4
–
P0
7
pull-up control bit
P3
0
–
3
pull-up control bit
P3
4
pull-up control bit
Disable
P3
7
pull-up control bit
b7 b0
0 : Pull-up Off
1 : Pull-up On
Note :
Pins set to output ports are disconnected from pull-up control.
Port P1P3 control register
(P1P3C: address 0017
16
, initial value: 00
16
)
b7 b0
P3
7
/INT
0
input level selection bit
0 : CMOS level
1 : TTL level
P3
4
/INT
1
input level selection bit
0 : CMOS level
1 : TTL level
P1
0
,P1
2
input level selection bit
0 : CMOS level
1 : TTL level
Disable
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 754-4.47M | 制造商:OSCILENT 制造商全稱:Oscilent Corporation 功能描述:Ceramic Trap Double/Triple Peak |
| 754-4.6M | 制造商:OSCILENT 制造商全稱:Oscilent Corporation 功能描述:Ceramic Trap Double/Triple Peak |
| 754-4007-0 | 制造商:ROCK 功能描述: |
| 75-440-6 | 制造商:ATM 制造商全稱:ATM 功能描述:STANDARD GAIN HORN |
| 75-440-X | 制造商:ATM 制造商全稱:ATM 功能描述:HORN MOUNT APPLICATIONS |
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