參數(shù)資料
型號(hào)： 7513
英文描述： 7513 Group Datasheet Datasheet 1067K/FEB.06.01
中文描述： 7513組數(shù)據(jù)表數(shù)據(jù)表1067K/FEB.06.01
文件頁(yè)數(shù)： 28/66頁(yè)
文件大?。?/td> 1067K
代理商： 7513
27
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7513 Group
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register. The timer
latch value is not affected by a change of the count source. How-
ever, because changing the count source may cause an
inadvertent count down of the timer. Therefore, rewrite the value
of timer whenever the count source is changed.
G
Timer 2 write control
If the timer 2 write control bit is
“
0
”
, when the value is written in the
address of timer 2, the value is loaded in the timer 2 and the latch
at the same time.
If the timer 2 write control bit is
“
1
”
, when the value is written in the
address of timer 2, the value is loaded only in the latch. The value
in the latch is loaded in timer 2 after timer 2 underflows.
G
Timer 2 output control
When the timer 2 (T
OUT
) is output enabled, an inversion signal
from the T
OUT
pin is output each time timer 2 underflows.
In this case, set the port shared with the T
OUT
pin to the output.
I
Notes on timer 1 to timer 3
When the count source of timer 1 to 3 is changed, the timer count-
ing value may be changed large because a thin pulse is generated
in count input of timer. If timer 1 output is selected as the count
source of timer 2 or timer 3, when timer 1 is written, the counting
value of timer 2 or timer 3 may be changed large because a thin
pulse is generated in timer 1 output.
Therefore, set the value of timer in the order of timer 1, timer 2
and timer 3 after the count source selection of timer 1 to 3.
Fig. 22 Structure of timer 123 mode register
Timer 123 mode register
(T123M :address 0029
16
)
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T
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output enabled
Timer 2 write control bit
0 : Write data in latch and counter
1 : Write data in latch only
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output control bit
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