
22
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7513 Group
Fig. 16 Interrupt control
Fig. 17 Structure of interrupt-related registers
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A
16
)
IN
I
N
I
N
A
T
0
T
1
T
2
D
T
i
i
i
i
n
n
n
n
t
t
t
t
e
e
e
e
r
r
r
r
r
r
r
r
u
u
u
u
p
p
p
p
t
t
t
t
e
e
e
e
d
d
d
d
g
g
g
g
e
e
e
e
s
s
s
s
e
e
e
e
l
l
l
l
e
e
e
e
c
c
c
c
t
t
t
t
i
i
i
i
o
o
o
o
n
n
n
n
b
b
b
b
i
i
i
i
t
t
t
t
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
In
(IREQ1 : address 003C
16
)
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
1
INT
0
interrupt request bit
INT
1
interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
In
(ICON1 : address 003E
16
)
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
IN
I
N
S
S
T
T
T
T
T
0
T
1
e
r
e
r
i
m
i
m
i
m
i
m
i
i
l
l
r
r
r
r
n
n
t
t
/
/
e
e
O
O
i
i
r
r
r
r
1
1
n
i
n
n
n
u
u
t
e
t
e
t
e
t
e
p
p
r
e
t
r
r
r
r
r
t
t
c
e
e
e
n
u
u
u
r
u
n
n
i
s
p
p
p
p
a
a
v
m
t
t
t
t
b
b
e
l
l
i
n
n
n
n
e
e
n
i
a
a
a
a
t
b
b
e
t
b
b
b
b
i
i
r
e
l
l
l
e
l
e
t
t
i
i
e
e
e
e
a
a
I
I
X
Y
2
3
t
r
r
u
r
b
b
b
b
p
u
t
t
e
n
e
a
n
b
a
l
e
l
b
i
t
i
a
r
r
r
i
n
p
i
t
i
t
i
t
i
t
b
e
b
t
i
e
e
e
e
e
e
0 : No interrupt request issued
1 : Interrupt request issued
Interrupt request register 2
(I
E
Q
2
:
a
d
d
r
CNTR
0
interrupt request bit
CNTR
1
interrupt request bit
Timer 1 interrupt request bit
INT
2
interrupt request bit
Serial I/O2 interrupt request bit
Key input interrupt request bit
ADT/AD conversion interrupt request bit
Not used (returns
“
0
”
when read)
R
e
s
s
0
0
3
D
1
6
)
In
(ICON2 : address 003F
16
)
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
C
C
T
I
N
S
K
A
N
(
D
N
N
i
T
T
e
R
0
R
1
r
i
n
a
l
i
n
T
/
A
t
u
o
n
i
i
e
/
O
p
u
D
s
e
o
t
n
n
i
n
r
t
t
e
e
t
e
r
u
2
i
n
c
o
d
(
w
r
r
r
r
r
p
i
n
t
n
e
t
e
u
u
r
u
t
t
e
v
t
u
“
p
p
p
e
e
r
r
e
r
1
t
t
t
e
e
e
a
u
p
s
i
n
s
”
n
n
n
b
p
t
o
“
t
o
a
a
a
l
e
t
e
n
0
t
b
b
b
e
n
i
n
”
h
l
l
e
e
l
e
b
n
a
t
w
i
s
b
b
b
i
i
t
t
i
m
T
2
e
r
e
y
D
o
1
t
I
t
n
r
r
u
r
i
a
b
e
h
b
t
i
b
l
e
r
r
e
i
l
e
u
n
t
.
b
i
t
t
r
i
t
t
b
p
)
e
a
n
d
a
)
b
l
e
b
i
t
r
i
e
r
0 : Interrupts disabled
1 : Interrupts enabled
0
1
:
F
R
a
i
l
l
i
i
n
n
g
g
e
e
d
d
g
g
e
e
a
a
c
c
t
i
i
v
v
e
e
:
s
t
b
7
b
0
b
7
b
0
b7
b
0
b7
b0
K
(K
e
y
C
i
n
:
p
a
u
d
t
d
c
r
o
e
n
s
t
r
o
0
l
0
r
1
e
5
1
g
i
6
)
s
t
e
r
P2
0
trigger valid bit
P2
1
trigger valid bit
P2
2
trigger valid bit
P2
3
trigger valid bit
P2
4
trigger valid bit
P2
5
trigger valid bit
P2
6
trigger valid bit
P2
7
trigger valid bit
0 : Trigger invalid
1 : Trigger valid
I
s
b7
b0
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
Set the corresponding interrupt enable bit to
“
0
”
(disabled).
Set the interrupt edge selection bit (active edge switch bit) or
the interrupt source selection bit to
“
1
”
.
Set the corresponding interrupt request bit to
“
0
”
after 1 or more
instructions have been executed.
Set the corresponding interrupt enable bit to
“
1
”
(enabled).