參數(shù)資料
型號(hào): 74LV175
廠商: NXP Semiconductors N.V.
英文描述: Quad D-type flip-flop with reset;positive-edge trigger(上升沿觸發(fā),帶復(fù)位的四D觸發(fā)器)
中文描述: 四D型觸發(fā)器的復(fù)位觸發(fā)器,積極邊緣觸發(fā)(上升沿觸發(fā),帶復(fù)位的四?觸發(fā)器)
文件頁數(shù): 7/13頁
文件大?。?/td> 119K
代理商: 74LV175
Philips Semiconductors
Product specification
74LV175
Quad D-type flip-flop with reset; positive-edge trigger
1998 May 20
7
AC WAVEFORMS
V
M
= 1.5 V at V
CC
2.7 V;
V
M
= 0.5 V
×
V
CC
at V
CC
<
2.7 V.
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
SV00604
1/f
max
t
PLH
t
PHL
t
PLH
t
W
t
PHL
V
M
VM
V
M
CP INPUT
Q
n
OUTPUT
V
I
GND
V
OH
V
OH
V
OL
V
OL
Qn OUTPUT
Figure 1. Clock (CP) to outputs (Q
n
, Q
n
) propagation delays,
the clock pulse width and the maximum clock pulse frequency.
SV00605
V
M
MR INPUT
CP INPUT
V
I
V
I
GND
GND
VOL
V
OL
V
OH
V
OH
Q
n
OUTPUT
Q
n
OUTPUT
V
M
V
M
V
M
t
rem
t
PHL
t
PLH
t
W
Figure 2. Master reset (MR) pulse width,
the master reset to outputs (Q
n
, Q
n
) propagation delay
and master reset to clock (CP) removal time.
SV00606
V
M
CP INPUT
GND
V
I
V
I
V
OH
V
OH
V
OL
GND
D
n
INPUT
Q
n
OUTPUT
Q
n
OUTPUT
V
M
V
M
V
M
t
h
t
h
t
su
t
su
V
OL
The shaded areas indicate when the input is permitted to change for
predictable output performance.
Figure 3. Data set-up and hold times for data input (D
n
).
TEST CIRCUIT
PULSE
GENERATOR
R
T
V
I
D.U.T.
V
O
C
L
R
L
= 1k
V
CC
Test Circuit for switching times
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitance
V
CC
V
I
< 2.7V
V
CC
TEST
t
PLH/
t
PHL
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
50pF
SV00901
2.7–3.6V
2.7V
Figure 4. Load circuitry for switching times.
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