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參數(shù)資料
| 型號： | 74LV175 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Quad D-type flip-flop with reset;positive-edge trigger(上升沿觸發(fā),帶復(fù)位的四D觸發(fā)器) |
| 中文描述： | 四D型觸發(fā)器的復(fù)位觸發(fā)器，積極邊緣觸發(fā)（上升沿觸發(fā)，帶復(fù)位的四?觸發(fā)器） |
| 文件頁數(shù)： | 2/13頁 |
| 文件大小： | 119K |
| 代理商： | 74LV175 |
Philips Semiconductors
Product specification
74LV175
Quad D-type flip-flop with reset; positive-edge trigger
2
1998 May 20
853–1926 19422
FEATURES
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical V
OLP
(output ground bounce) < 0.8 V at V
CC
= 3.3 V,
T
amb
= 25
°
C
Typical V
OHV
(output V
OH
undershoot) > 2 V at V
CC
= 3.3 V,
T
amb
= 25
°
C
Four edge-triggered D flip-flops
Output capability: standard
I
CC
category: MSI
DESCRIPTION
The 74LV175 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT175.
The 74LV175 has four edge-triggered, D-type flip-flops with
individual D inputs and both Q and Q outputs. The common clock
(CP) and master reset (MR) inputs load and reset (clear) all flip-flops
simultaneously.
The register is fully edge-triggered. The state of each D input, one
set-up time prior to the LOW-to-HIGH clock transition, is transferred
to the corresponding output (Q
n
) of the flip-flop.
All Q
n
outputs will be forced LOW independently of clock or data
inputs by a LOW voltage level on the MR input.
The device is useful for applications where both the true and
complement outputs are required and the clock and master reset are
common to all storage elements.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns
SYMBOL
Propagation delay
CP to Q
n,
Q
n
MR to Q
n,
Q
n
f
max
Maximum clock frequency
C
I
Input capacitance
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
C
L
= 15 pF;
V
CC
= 3.3 V
16
14
77
ns
ns
MHz
3.5
pF
C
PD
Power dissipation capacitance per flip-flop
V
CC
= 3.3 V
V
I
CC1
32
pF
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
V
CC2
f
i
(C
L
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC2
f
o
) = sum of the outputs.
V
CC2
f
o
) where:
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
74LV175 N
74LV175 N
SOT38-4
16-Pin Plastic SO
74LV175 D
74LV175 D
SOT109-1
16-Pin Plastic SSOP Type II
74LV175 DB
74LV175 DB
SOT338-1
16-Pin Plastic TSSOP Type I
74LV175 PW
74LV175PW DH
SOT403-1
PIN CONFIGURATION
SV00596
1
2
3
4
5
6
MR
Q
0
Q
0
D
0
D
1
Q
1
VCC
Q
3
Q
3
16
15
14
13
12
11
7
8
GND
Q
2
CP
10
9
Q
1
D
3
D
2
Q
2
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1
MR
Master reset input (active LOW)
2, 7, 10, 15
Q
0
to Q
3
Flip-flop outputs
3, 6, 11, 14
Q
0
to Q
3
Complementary flip-flop outputs
4, 5, 12, 13
D
0
to D
3
Data inputs
8
GND
Ground (0 V)
9
CP
Clock input
(LOW-to-HIGH, edge-triggered)
16
V
CC
Positive supply voltage
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LV20PW | Dual 4-input NAND gate |
| 74LV20PWDH | Sensors |
| 74LV20DB | Dual 4-input NAND gate |
| 74LV20 | Dual 4-input NAND gate |
| 74LV20D | Dual 4-input NAND gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LV175D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad D-Type Flip-Flop |
| 74LV175DB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad D-Type Flip-Flop |
| 74LV175DB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad D-Type Flip-Flop |
| 74LV175D-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad D-Type Flip-Flop |
| 74LV175N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad D-Type Flip-Flop |
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