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參數(shù)資料
| 型號： | 74LV109PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual JK flip-flop with set and reset; positive-edge trigger |
| 中文描述： | LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 124K |
| 代理商： | 74LV109PWDH |
Philips Semiconductors
Product specification
74LV109
Dual JK flip-flop with set and reset; positive-edge trigger
1998 Apr 20
6
AC CHARACTERISTICS (Continued)
GND
=
0V; t
r
=
t
f
≤
2.5ns; C
L
=
50pF; R
L
=
1K
CONDITION
LIMITS
SYMBOL
PARAMETER
WAVEFORM
–40 to +85
°
C
TYP
1
75
26
19
17
2
75
26
19
15
2
70
24
18
13
2
12
9
7
2
9
6
5
2
35
12
9
7
2
30
10
8
6
2
–5
–2
–1
0
2
40
58
70
2
–40 to +125
°
C
MIN
UNIT
V
CC
(V)
1.2
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
2.0
2.7
3.0 to 3.6
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
2.0
2.7
3.0 to 3.6
MIN
MAX
MAX
t
PHL
Propagation delay
nS
D
to nQ
Figure 2
46
36
29
60
44
35
ns
y
t
PHL
Propagation delay
nR
D
to nQ
Figure 2
46
36
29
60
44
35
ns
y
t
PLH
Propagation delay
nR
D
to nQ
Figure 2
44
33
26
54
40
32
ns
Clock pulse width
HIGH or LOW
34
25
20
34
25
20
41
30
24
41
30
24
t
W
Figure 1
ns
Set or reset pulse
width HIGH or LOW
t
W
Figure 2
ns
t
rem
Removal time
nS
D,
nR
D
to nCP
Figure 2
24
18
14
29
21
17
ns
t
su
Set-up time
nJ, nK to CP
Figure 1
22
16
13
26
19
15
ns
t
h
Hold time
nJ, nK to nCP
Figure 1
5
5
5
14
19
24
5
5
5
12
16
20
ns
Maximum clock
pulse frequency
f
max
Figure 1
MHz
NOTES:
1. Unless otherwise stated, all typical values are measured at T
amb
= 25
°
C
2. Typical values are measured at V
CC
= 3.3 V.
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