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參數(shù)資料
| 型號： | 74LV109PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual JK flip-flop with set and reset; positive-edge trigger |
| 中文描述： | LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 124K |
| 代理商： | 74LV109PWDH |
Philips Semiconductors
Product specification
74LV109
Dual JK flip-flop with set and reset; positive-edge trigger
2
1998 Apr 20
853-1986 19255
FEATURES
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical V
OLP
(output ground bounce) < 0.8 V at V
CC
= 3.3 V,
T
amb
= 25
°
C
Typical V
OHV
(output V
OH
undershoot) > 2 V at V
CC
= 3.3 V,
T
amb
= 25
°
C
Output capability: standard
I
CC
category: flip-flops
DESCRIPTION
The 74LV109 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT109.
The 74LV109 is a dual positive-edge triggered JK-type flip-flop
featuring individual J, K inputs, clock (CP) inputs, set (S
D
) and reset
(R
D
) inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input.
The J and K inputs control the state changes of the flip-flops as
described in the mode select function table. The J and K inputs must
be stable one set-up time prior to the LOW-to-HIGH clock transition
for predictable operation.
The JK design allows operation as a D-type flip-flop by tying the
J and K inputs together.
Schmitt-trigger action in the clock input makes the circuit highly
tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
=t
f
≤
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
nCP to nQ, nQ
nS
D
to nQ, nQ
nR
D
to nQ, nQ
Maximum clock frequency
C
L
= 15 pF;
V
CC
= 3.3 V
14
12
12
ns
f
max
C
I
C
PD
77
MHz
Input capacitance
3.5
pF
Power dissipation capacitance per flip-flop
V
I
= GND to V
CC1
20
pF
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
×
V
CC2
×
f
i
Σ
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
74LV109 N
74LV109 N
SOT38-4
16-Pin Plastic SO
74LV109 D
74LV109 D
SOT109-1
16-Pin Plastic SSOP Type II
74LV109 DB
74LV109 DB
SOT338-1
16-Pin Plastic TSSOP Type I
74LV109 PW
74LV109PW DH
SOT403-1
PIN CONFIGURATION
SV00517
1RD
1K
1CP
1SD
VCC
2RD
2J
2K
2CP
2SD
2Q
2Q
1J
1Q
1Q
GND
14
13
12
11
10
9
8
1
2
3
4
5
6
7
16
15
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1, 15
1R
D
, 2R
D
Asynchronous reset input
(active LOW)
2, 14, 3, 13
1J, 2J,
1K, 2K
Synchronous inputs; flip-flops 1 and 2
4, 12
1CP, 2CP
Clock input (LOW-to-HIGH,
edge-triggered)
Asynchronous set inputs
(active LOW)
True flip-flop outputs
5, 11
1S
D,
2S
D
6, 10
1Q, 2Q
7, 9
1Q, 2Q
Complement flip-flop outputs
8
GND
Ground (0 V)
16
V
CC
Positive supply voltage
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LV10PW | Triple 3-input NAND gate |
| 74LV10PWDH | Triple 3-input NAND gate |
| 74LV10D | Triple 3-input NAND gate |
| 74LV10DB | Triple 3-input NAND gate |
| 74LV10N | Triple 3-input NAND gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LV109PW-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
| 74LV10D | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple 3-input NAND gate |
| 74LV10DB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple 3-input NAND gate |
| 74LV10DB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Triple 3-input NAND Gate |
| 74LV10D-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Triple 3-input NAND Gate |
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