參數(shù)資料
型號(hào)： 74HCT7030
廠商： NXP Semiconductors N.V.
英文描述： 9-bit x 64-word FIFO register;3-state(64字 x9-位 先進(jìn)先出寄存器；（三態(tài)）)
中文描述： 9位x 64字FIFO寄存器，3態(tài)（64字X9熱賣，位先進(jìn)先出寄存器（三態(tài)））
文件頁(yè)數(shù)： 21/22頁(yè)
文件大?。?/td> 172K
代理商： 74HCT7030
December 1990
21
Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
74HC/HCT7030
Fig.22 Waveforms showing the functionality and intercommunication between two FIFOs (refer to Fig.19).
Sequence 1 (Both FIFOs empty, starting shift-in process):
After a MR pulse has been applied FIFO
and FIFO
are empty. The DOR flags of FIFO
and FIFO
go
LOW due to no valid data being present at the outputs. The DIR flags are set HIGH due to the FIFOs being
ready to accept data. SO
is held HIGH and two SI
A
pulses are applied (1). These pulses allow two data
words to ripple through to the output stage of FIFO
and to the input stage of FIFO
(2). When data arrives
at the output of FIFO
, a DOR
pulse is generated (3). When SO
goes LOW, the first bit is shifted out and
a second bit ripples through to the output after which DOR
B
goes HIGH (4).
Sequence 2 (FIFO
runs full):
After the MR pulse, a series of 64 SI pulses are applied. When 64 words are shifted in, DIR
B
remains LOW
due to FIFO
B
being full (5). DOR
A
goes LOW due to FIFO
A
being empty.
Sequence 3 (FIFO
runs full):
When 65 words are shifted in, DOR
remains HIGH due to valid data remaining at the output of FIFO
.
Q
remains HIGH, being the polarity of the 65th data word (6). After the 128th SI pulse, DIR remains LOW
and both FIFOs are full (7). Additional pulses have no effect.
Sequence 4 (Both FIFOs full, starting shift-out process):
SI
is held HIGH and two SO
pulses are applied (8). These pulses shift out two words and thus allow two
empty locations to bubble-up to the input stage of FIFO
, and proceed to FIFO
(9). When the first empty
location arrives at the input of FIFO
, a DIR
pulse is generated (10) and a new word is shifted into FIFO
A
.
SI
A
is made LOW and now the second empty location reaches the input stage of FIFO
A
, after which
DIR
A
remains HIGH (11).
Sequence 5 (FIFO
runs empty):
At the start of sequence 5 FIFO
contains 63 valid words due to two words being shifted out and one word
being shifted in in sequence 4. An additional series of SO
pulses are applied. After 63 SO
B
pulses, all
words from FIFO
A
are shifted into FIFO
B
. DOR
A
remains LOW (12).
Sequence 6 (FIFO
B
runs empty):
After the next SO
pulse, DIR
B
remains HIGH due to the input stage of FIFO
being empty (13). After
another 63 SO
pulses, DOR
remains LOW due to both FIFOs being empty (14). Additional SO
B
pulses
have no effect. The last word remains available at the output Q
n
.
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74HCT7030D,112 功能描述:寄存器 64 WORD X 9-BIT FIFO RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
74HCT7030D,118 功能描述:寄存器 64 WORD X 9-BIT FIFO RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
74HCT7030D-T 功能描述:寄存器 64 WORD X 9-BIT FIFO RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
74HCT7030N 功能描述:寄存器 64 WORD X 9-BIT FIFO RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
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