參數(shù)資料
型號(hào)： 74F8966
廠商： NXP Semiconductors N.V.
英文描述： 9-Bit address/data Futurebus transceiver, ADT
中文描述： 9位地址/數(shù)據(jù)Futurebus收發(fā)器，ADT的
文件頁數(shù)： 6/11頁
文件大小： 119K
代理商： 74F8966
Philips Semiconductors FAST Products
Product specification
74F8965/74F8966
9-Bit address/data Futurebus transceiver, ADT
December 19, 1990
6
FUNCTION TABLE FOR 74F8965
INPUTS
LATCH
OUTPUTS
OPERATING MODE
AIn
Bn*
OEB0
OEB1
LS
OEA
LE
STATE
An
Bn
L
–
H
L
H
L
X
X
input
H**
An to Bn bypass latch
H
–
H
L
H
L
X
X
input
L
L
–
H
L
L
L
L
H
input
H**
An to Bn transparent latch
H
–
H
L
L
L
L
L
input
L
l
–
H
L
L
L
↑
H
input
H**
An to Bn latch and read
h
–
H
L
L
L
↑
L
input
L
–
–
H
L
L
H
H
H
L
H**
An to Bn outputs latched and read
–
–
H
L
L
H
H
L
H
L
(preconditioned latch)
X
–
H
L
L
L
H
NC
input
L
An to Bn hold
X
X
L
X
X
X
X
X
X
H**
Disable Bn outputs
X
X
X
H
H
X
X
X
X
H**
–
L
L
H
H
H
X
X
H
input
Bn to An
–
H
L
H
H
H
X
X
L
input
–
X
X
X
X
L
X
X
Z
X
Disable An outputs
Notes to function table for 74F8965
1. H =
High voltage level
2. h =
High voltage level one setup time prior to the low–to–high LE transition
3. L
=
Low voltage level
4. l
=
Low voltage level one setup time prior to the low–to–high LE transition
5. NC=
No change
6. X =
Don’t care
7. Z =
High impedance ”off’ state
8. –
=
Input not externally driven
9.
↑
=
Low–to–high transition
10.H**=
Goes to level of pullup voltage.
11.B* =
Precaution should be taken to insure B inputs do not float. If they do they are equal to low state.
FUNCTION TABLE FOR 74F8966
INPUTS
LATCH
OUTPUTS
OPERATING MODE
AIn
Bn*
OEB0
OEB1
IAREQ
LS
OEA
LE
STATE
An
Bn
IAMC
L
–
H
L
L
H
L
X
X
input
H**
H**
An to Bn bypass latch
H
–
H
L
L
H
L
X
X
input
L
H**
L
–
H
L
L
L
L
L
H
input
H**
H**
An to Bn transparent latch
H
–
H
L
L
L
L
L
L
input
L
H**
l
–
H
L
L
L
L
↑
↑
H
input
H**
H**
An to Bn latch and read
h
–
H
L
L
L
L
L
input
L
H**
–
–
H
L
L
L
H
H
H
L
H**
H**
An to Bn outputs latched and read
–
–
H
L
L
L
H
H
L
H
L
H**
(preconditioned latch)
X
–
H
L
L
L
L
H
NC
input
NC
H**
An to Bn hold
X
X
L
X
X
X
X
X
X
X
H**
H**
Disable Bn outputs
X
X
X
H
H
H
X
X
X
X
H**
H**
–
L
L
H
H
H
H
X
X
H
input
H**
Bn to An
–
H
L
H
H
H
H
X
X
L
input
H**
–
Bn
L
H
H
↓
*
↓
*
H
H
Bn
Z
Bn
L
Latch Bn data idle arbitration request
–
Bn
L
H
H
H
H
Bn
Z
Bn
H**
(preconditioned latch)
–
X
X
X
X
X
L
X
X
Z
X
X
Disable An outputs
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