參數(shù)資料
型號(hào): 74F8966
廠商: NXP Semiconductors N.V.
英文描述: 9-Bit address/data Futurebus transceiver, ADT
中文描述: 9位地址/數(shù)據(jù)Futurebus收發(fā)器,ADT的
文件頁數(shù): 3/11頁
文件大小: 119K
代理商: 74F8966
Philips Semiconductors FAST Products
Product specification
74F8965/74F8966
9-Bit address/data Futurebus transceiver, ADT
December 19, 1990
3
LOGIC SYMBOL
A0 A1 A2 A3 A4 A5 A6 A7 A8
Logic V
= Pin 3, 21
Logic GND = Pin 5, 7, 9, 11, 14, 16, 18, 20
74F8965
1
44
23
22
2
OEB0
OEB1
LS
LE
OEA
4
6
8
10 12 13 15 17 19
B0 B1 B2 B3 B4 B5 B6 B7 B8
41 39 37 35 33 31 29 27 25
A0 A1 A2 A3 A4 A5 A6 A7 A8
74F8966
1
44
23
22
2
20
OEB0
OEB1
IAREQ
LE
OEA
IAMC
4
6
8
10 12 13 15 17 19
B0 B1 B2 B3 B4 B5 B6 B7 B8
41 39 37 35 33 31 29 27 25
Logic V
= Pin 3, 21
Logic GND = Pin 5, 7, 9, 11, 14, 16, 18
PIN DESCRIPTION
SYMBOL
PINS
TYPE
NAME AND FUNCTION
A0 – A8
4, 6, 8, 10, 12, 13, 15, 17, 19
I/O
Data inputs/TTL 3–state outputs
B0 – B8
41, 39, 37, 35, 33, 31, 29, 27, 25
I/O
Data inputs / open collector outputs, high current drives.
OEB0
1
Input
Output enable input. Enables the B outputs when high.
OEB1
44
Input
Output enable input. Enables the B outputs when low.
OEA
2
Input
Output enable input. Enables the A outputs when high.
LE
22
Input
Latch enable input. Enables latch when low.
LS
23
Input
Latch select input. Selects latch when low (74F8965).
IAREQ
23
Input
Idle arbitration request input (74F8966).
IAMC
20
Output
Idle arbitration/multiple competitors output (open collector output) (74F8966).
Bus GND
26, 28, 30, 32, 34, 36, 38, 40, 42
Ground
Bus ground (0V)
Logic GND
5, 7, 9, 11, 14, 16, 18, 20 (74F8965)
Ground
Logic ground (0V)
Bus V
CC
Logic V
CC
24, 43
Power
Positive supply voltages
3, 21
Power
Positive supply voltages
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