參數(shù)資料
型號: 73S1210F-68MR/F/PG
廠商: Maxim Integrated
文件頁數(shù): 93/126頁
文件大?。?/td> 0K
描述: IC SOC SMART CARD READER 68QFN
標(biāo)準(zhǔn)包裝: 2,500
系列: *
DS_1210F_001
73S1210F Data Sheet
Rev. 1.4
69
1.7.15 Smart Card Interface Function
The 73S1210F integrates one ISO-7816 (T=0, T=1) UART, one complete ICC electrical interface as well
as an external smart card interface to allow multiple smart cards to be connected using the Teridian 8010
family of interface devices. Figure 14 shows the simplified block diagram of the card circuitry (UART +
interfaces), with detail of dedicated XRAM registers.
Figure 14: Smart Card Interface Block Diagram
Card interrupts are managed through two dedicated registers: SCIE (Interrupt Enable to define which
interrupt is enabled) and SCInt (Interrupt status). They allow the firmware to determine the source of an
interrupt, that can be a card insertion / removal, card power fault, or a transmission (TX) or reception (RX)
event / fault. It should be noted that even when card clock is disabled, an ICC interrupt can be generated
Direct
Mode
Card
Insertion
Activation /
Deactivation
Sequencer
VCC
Buffer / Level
Shifter
RST
Buffer / Level
Shifter
CLK
I/O
Buffer / Level
Shifter
C4
Buffer / Level
Shifter
C8
Buffer / Level
Shifter
VCC Card
Generation
ICC Event
ICC Pwr_event
I/O ICC#1
I/O
E
x
t.
IC
C
CLK ICC
CLKExt. ICC
Card Clock
Management
7.2MHz
SCCLK/
SCSCLK
PRES
Serial
UART
Internal ICC Interface
SCSel
UART
T=0 T=1
RLength
STSTO
ATRMsB/LsB
BGT/EGT
SRXData
SRXCtl
STXData
STXCtl
SCPrtcol
SCCtl
FDReg
SByteCtl
SParCtl
Card Interrupt
Management
SCInt
SCIE
External ICC Interface
B
yp
ass
M
o
d
e
XRAM Registers
VccCtl/
VccTMR
SCCLK/SCSCLK
Timers
2-Byte
Tx FIFO
2-Byte
Rx FIFO
Card and
Mode
Selection
TX
RX
SCDir
SCECtl
BGT0/1/2/3/
CWT0/1
SIO
SCLK
SCCLK
SCSCLK
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