參數(shù)資料
型號(hào)： 73S1210F-68MR/F/PG
廠商： Maxim Integrated
文件頁數(shù)： 69/126頁
文件大?。?/td> 0K
描述： IC SOC SMART CARD READER 68QFN
標(biāo)準(zhǔn)包裝： 2,500
系列： *
DS_1210F_001
73S1210F Data Sheet
Rev. 1.4
47
1.7.8
WD Timer (Software Watchdog Timer)
The software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles.
After a reset, the watchdog timer is disabled and all registers are set to zero. The watchdog consists of a
16-bit counter (WDT), a reload register (WDTREL), prescalers (by 2 and by 16), and control logic. Once
the watchdog starts, it cannot be stopped unless the internal reset signal becomes active.
WD Timer Start Procedure: The WDT is started by setting the SWDT flag. When the WDT register
enters the state 0x7CFF, an asynchronous WDTS signal will become active. The signal WDTS sets bit 6
in the IP0 register and requests a reset state. WDTS is cleared either by the reset signal or by changing
the state of the WDT timer.
Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request
signal from becoming active. This requirement imposes an obligation on the programmer to issue two
instructions. The first instruction sets WDT and the second instruction sets SWDT. The maximum delay
allowed between setting WDT and SWDT is 12 clock cycles. If this period has expired and SWDT has
not been set, WDT is automatically reset, otherwise the watchdog timer is reloaded with the content of
the WDTREL register and WDT is automatically reset.
Interrupt Enable 0 Register (IEN0): 0xA8
0x00
Table 43: The IEN0 Register
MSB
LSB
EAL
WDT
ET2
ES0
ET1
EX1
ET0
EX0
Bit
Symbol
Function
IEN0.7
EAL
EAL = 0 – disable all interrupts.
IEN0.6
WDT
Watchdog timer refresh flag.
Set to initiate a refresh of the watchdog timer. Must be set directly before
SWDT is set to prevent an unintentional refresh of the watchdog timer. WDT
is reset by hardware 12 clock cycles after it has been set.
IEN0.5
–
IEN0.4
ES0
ES0 = 0 – disable serial channel 0 interrupt.
IEN0.3
ET1
ET1 = 0 – disable timer 1 overflow interrupt.
IEN0.2
EX1
EX1 = 0 – disable external interrupt 1.
IEN0.1
ET0
ET0 = 0 – disable timer 0 overflow interrupt.
IEN0.0
EX0
EX0 = 0 – disable external interrupt 0.
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73S1210F-EB 功能描述:開發(fā)板和工具包 - 8051 73S1210F Eval Brd (Doc. Cd, Cable) RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評(píng)估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓:
73S1210F-EB-Lite 功能描述:開發(fā)板和工具包 - 8051 73S1210F Eval Brd Lite w/Doc Cd, Cable RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評(píng)估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓:
73S1210F-EB-LiteMS 功能描述:開發(fā)板和工具包 - 8051 73S1210F Eval Brd Lite + Multi Sam RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評(píng)估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓:
73S1215F 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:80515 System-on-Chip with USB, ISO 7816 / EMV, PINpad and More
73S1215F-44IM/F 功能描述:8位微控制器 -MCU 80515 SoC w/USB & PINpad RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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