參數(shù)資料
型號: 73M1866B-IM/F
廠商: Maxim Integrated Products
文件頁數(shù): 49/88頁
文件大?。?/td> 0K
描述: MICRODAA SGL PCM HIGHWAY 42-QFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 260
系列: MicroDAA™
功能: 數(shù)據(jù)存取裝置(DAA)
接口: PCM,串行,SPI
電路數(shù): 1
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 42-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 42-QFN(8x8)
包裝: 管件
包括: PCM 通路
DS_1x66B_001
73M1866B/73M1966B Data Sheet
Rev. 1.6
53
Function
Mnemonic
Register
Location
Type
Description
PCODE
0x23[5:2]
W
PCM Clock Code
The default state of PCODE out of reset is 0000. In PCM Slave
Mode at reset, the device will attempt to automatically detect the
correct frequency of PCLK. If the PCLK frequency is different from
those listed in the table below or an incorrect PCODE value is
written, the PLL will not lock (LOCKDET 0x0D[7] == 0). To modify
the value of PCODE, first write a value of 0000 and then write the
required PCODE value. Toggling of the MASTER bit 0x23[6]
(0
1 0) with a PCODE of 0000 will also restart the automatic
PCLK frequency detection function.
PCLK
Frequency
PCODE [3:0]
256 kHz
0001
512 kHz
0010
768 kHz
0011
1.024 MHz
0100
1.536 MHz
0101
1.544 MHz
0110
2.048 MHz
0111
3.088 MHz
1000
4.096 MHz
1001
6.176 MHz
1010
8.192 MHz
1011
RCS
0x22[5:3]
W
Receive Clock Slot
These bits control the starting clock of the receive channel. The
clock slot value allows the adding of an offset of up to 7 (111) bits to
the time slot value. A value of 000 is zero offset.
RPOL
0x21[7]
W
Receive Polarity
0 = The receive PCM data is to be sampled on the falling edge of
PCLK. (Default)
1 = The receive PCM data is to be sampled on the rising edge of
PCLK.
RTS
0x21[6:0]
W
Receive Time Slot
Selects the time slot number on the PCM highway for the receiver.
The maximum number of 8-bit time slots is 128 (with a PCLK
frequency of 8.192 MHz). A value of 0000000 is time slot zero and
1111111 is time slot 128. The default is 0000000.
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