參數(shù)資料
型號： 73M1866B-IM/F
廠商： Maxim Integrated Products
文件頁數(shù)： 39/88頁
文件大小： 0K
描述： MICRODAA SGL PCM HIGHWAY 42-QFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 260
系列： MicroDAA™
功能： 數(shù)據(jù)存取裝置（DAA）
接口： PCM，串行，SPI
電路數(shù)： 1
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 42-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 42-QFN（8x8）
包裝： 管件
包括： PCM 通路
73M1866B/73M1966B Data Sheet
DS_1x66B_001
44
Rev. 1.6
7.6
Call Progress Monitor
For
the purpose of monitoring activities on the line, a Call Progress Monitor is provided in the 73M1x66B.
This audio output contains both transmit and receive data with configurable levels.
7.7
16 kHz Operation of Call Progress Monitor
After switching from 8 kHz sampling rate to 16 kHz sampling rate, the SLEEP bit must be enabled then
disabled if the Call Progress Monitor function is used. After cycling the SLEEP bit, the Line-Side Device
registers (Registers 0x12 to 0x18) must be reconfigured.
7.8
Device Reset
For a correct reset of the 73M1x66B, the
RST signal must be asserted for a minimum period of 1 ms.
PCLK must be active for a minimum of 8 clock cycles before the
RST signal can be de-asserted. The
PLL locks to the PCLK after 20 PCM frames as defined by the occurrence of the Frame Sync Signal (FS).
This gives a minimum period of 3.5 ms from the assertion of
RST until the PLL is locked and normal
operations may occur, including access to all device registers and the transmission and reception of PCM
data samples. If PCLK changes frequency, then the PLL will lose lock so a stable clock must be used
during this reset period. If a PCLK frequency change is required after the reset, the user should
implement the procedure described for PCODE (Register 0x23 bits 2 to 5).
Function
Mnemonic
Register
Location
Type
Description
CMRXG
0x10[1:0]
W
Receive Path Gain Setting
00
0 dB (for full swing, AOUT=1.08 Vpk) (Default)
01
-6 dB
10
-12 dB
11
MUTE
CMTXG
0x10[3:2]
W
Transmit Path Gain Setting
00
0 dB (for full swing, AOUT=1.08 Vpk) (Default)
01
-6 dB
10
-12 dB
11
MUTE
CMVSEL
0x10[4]
W
Call Progress Monitor Voltage Reference Select
Quiescent DC voltage select at AOUT.
0 = 1.5 Vdc. (Default)
1 = VCC/2 Vdc.
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