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參數(shù)資料
| 型號： | 72841L10PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 4K X 9 BI-DIRECTIONAL FIFO, 6.5 ns, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 211K |
| 代理商： | 72841L10PF |
14
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION — When FIFO A (B) is in a Single
Device Configuration, the Read Enable 2
RENA2 (RENB2) control input
can be grounded (see Figure 14). In this configuration, the Write Enable 2/
Load WENA2/
LDA (WENB2/LDB) pin is set LOW at Reset so that the pin
operates as a control to load and read the programmable flag offsets.
Figure 15. Block diagram of the two FIFOs contained in one IDT72801/72811/
72821/72831/72841/72851 configured for an 18-bit width-expansion
WIDTH EXPANSION CONFIGURATION — Word width may be in-
creased simply by connecting the corresponding input control signals of
FIFOs A and B. A composite flag should be created for each of the endpoint
status flags
EFA and EFB, also FFA and FFB). The partial status flags
PAEA, PAFB, PAEA and PAFB can be detected from any one device.
Figure 15 demonstrates an 18-bit word width using the two FIFOs contained
in one IDT72801/72811/72821/72831/72841/72851. Any word width can
be attained by adding additional IDT72801/72811/72821/72831/72841/
72851s.
When these devices are in a Width Expansion Configuration, the Read
Enable 2 (
RENA2 and RENB2) control inputs can be grounded (see
Figure 15). In this configuration, the Write Enable 2/Load (WENA2/
LDA,
WENB2/
LDB) pins are set LOW at Reset so that the pin operates as a
control to load and read the programmable flag offsets.
Figure 14. Block Diagram of One of the IDT72801/72811/72821/72831/72841/72851's two FIFOs
configured as a single device
QA0 - QA8 (QB0 - QB8)
DA0 - DA8 (DB0 - DB8)
RSA (RSB)
RCLKA (RCLKB)
RENA1 (RENB1)
OEA (OEB)
EFA (EFB)
PAEA (PAEB)
RENA2 (RENB2)
WCLKA (WCLKB)
WENA1 (WENB1)
WENA2/
LDA (WENB2/LDB)
FFA (FFB)
PAFA (PAFB)
IDT
72801
72811
72821
72831
72841
72851
FIFO
A (B)
3034 drw 15
DATA IN
WRITE CLOCK
18
9
RSB
READ CLOCK
9
18
RENB2
RENA2
WRITE ENABLE
FFA
EFB
OUTPUT ENABLE
READ ENABLE
9
WRITE ENABLE/LOAD
FFB
EFA
RSA
RAM
ARRAY
B
256x9
512x9
1,024x9
2,048x9
4,096x9
8,192x9
RAM
ARRAY
A
256x9
512x9
1,024x9
2,048x9
4,096x9
8,192x9
DATA OUT
RCLKA
EMPTY FLAG
RENB1
RENA1
OEB
OEA1
RCLKB
WCLKA
WCLKB
WENA1
WENB1
DA0 - DA8
DB0 - DB8
QA0 - QA8
QB0 - QB8
WENA2/
LDA
2WENB2/
LDB
RESET
9
FULL FLAG
3034 drw 16
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 72841L10PF8 | 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72841L10PFG | 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72841L10PFG8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 4K x 9 x 2 64-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC QUAD DEPTH/WIDTH BI-DIR 4KX9X2 64TQFP - Tape and Reel |
| 72841L10TF | 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72841L10TF8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 4K x 9 x 2 64-Pin STQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC QUAD DEPTH/WIDTH BI-DIR 4KX9X2 64TQFP - Tape and Reel |
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