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參數(shù)資料
| 型號： | 72841L10PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 4K X 9 BI-DIRECTIONAL FIFO, 6.5 ns, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 211K |
| 代理商： | 72841L10PF |
IDT, IDT logo and the
SyncFIFO logo are trademarks of Integrated Device Technology, Inc.
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-3034/2
APRIL 2001
DUAL CMOS SyncFIFO
DUAL 256 x 9, DUAL 512 x 9,
DUAL 1,024 x 9, DUAL 2,048 x 9,
DUAL 4,096 x 9, DUAL 8,192 x 9
IDT72801
IDT72811
IDT72821
IDT72831
IDT72841
IDT72851
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
1
FEATURES:
The IDT72801 is equivalent to two IDT72201 256 x 9 FIFOs
The IDT72811 is equivalent to two IDT72211 512 x 9 FIFOs
The IDT72821 is equivalent to two IDT72221 1,024 x 9 FIFOs
The IDT72831 is equivalent to two IDT72231 2,048 x 9 FIFOs
The IDT72841 is equivalent to two IDT72241 4,096 x 9 FIFOs
The IDT72851 is equivalent to two IDT72251 8,192 x 9 FIFOs
Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
Ideal for prioritization, bidirectional, and width expansion
applications
10 ns read/write cycle time for the IDT72801/72811/72821/72831/
72841 (excluding the IDT72851)
15 ns read/write cycle time for the IDT72851
Separate control lines and data lines for each FIFO
Separate Empty, Full, Programmable Almost-Empty and Almost-
Full flags for each FIFO
Enable puts output data lines in high-impedance state
Space-saving 64-pin Thin Quad Flat Pack (TQFP) and Slim Thin
Quad Flatpack (STQFP)
Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
DESCRIPTION:
The IDT72801/72811/72821/72831/72841/72851 are dual synchronous
(clocked)FIFOs. ThedeviceisfunctionallyequivalenttotwoIDT72201/72211/
72221/72231/72241/72251 FIFOs in a single package with all associated
control, data, and flag lines assigned to separate pins.
Each of the two FIFOs (designated FIFO A and FIFO B) contained in the
IDT72801/72811/72821/72831/72841/72851 has a 9-bit input data port (DA0
- DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8, QB0 - QB8). Each
inputportiscontrolledbyafree-runningclock(WCLKA,WCLKB),andtwoWrite
Enable pins (
WENA1,WENA2,WENB1,WENB2). Dataiswrittenintoeachof
the two arrays on every rising clock edge of the Write Clock (WCLKA, WCLKB)
when the appropriate write enable pins are asserted.
The output port of each FIFO bank is controlled by its associated clock pin
(RCLKA, RCLKB) and two Read Enable pins (
RENA1, RENA2, RENB1,
RENB2).TheReadClockcanbetiedtotheWriteClockforsingleclockoperation
orthetwoclockscanrunasynchronousofoneanotherfordualclockoperation.
An Output Enable pin (
OEA, OEB) is provided on the read port of each FIFO
for three-state output control.
Each of the two FIFOs has two fixed flags, Empty (
EFA,EFB)andFull(FFA,
FFB). Twoprogrammableflags,Almost-Empty(PAEA,PAEB)andAlmost-Full
(
PAFA,PAFB),areprovidedforeachFIFObanktoimprovememoryutilization.
If not programmed, the programmable flags default to empty+7 for
PAEAand
PAEB, and full-7 for PAFA and PAFB.
TheIDT72801/72811/72821/72831/72841/72851architecturelendsitself
to many flexible configurations such as:
2-level priority data buffering
Bidirectional operation
Width expansion
Depth expansion
These FIFOs is fabricated using IDT's high-performance submicron
CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
WCLKA
WENA1
WENA2
DA0 - DA8
LDA
OFFSET REGISTER
INPUT REGISTER
RAM ARRAY
256 x 9, 512 x 9,
1024 x 9, 2048 x 9,
4096 x 9, 8192 x 9
WRITE CONTROL
LOGIC
WRITE POINTER
RESET LOGIC
OUTPUT REGISTER
OEA
RSA
QA0 - QA8
RCLKA
RENA1
RENA2
READ CONTROL
LOGIC
READ POINTER
FLAG
LOGIC
EFA
PAEA
PAFA
FFA
3034 drw 01
WCLKB
WENB1
WENB2
DB0 - DB8
LDB
OFFSET REGISTER
INPUT REGISTER
WRITE CONTROL
LOGIC
WRITE POINTER
RESET LOGIC
OUTPUT REGISTER
OEB
RSB
QB0 - QB8
RCLKB
RENB1
RENB2
READ CONTROL
LOGIC
READ POINTER
FLAG
LOGIC
EFB
PAEB
PAFB
FFB
RAM ARRAY
256 x 9, 512 x 9,
1024 x 9, 2048 x 9,
4096 x 9, 8192 x 9
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 72841L10PF8 | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72841L10PFG | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72841L10PFG8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 4K x 9 x 2 64-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC QUAD DEPTH/WIDTH BI-DIR 4KX9X2 64TQFP - Tape and Reel |
| 72841L10TF | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72841L10TF8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 4K x 9 x 2 64-Pin STQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC QUAD DEPTH/WIDTH BI-DIR 4KX9X2 64TQFP - Tape and Reel |
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