參數(shù)資料
型號: 71V416S10PHGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 256K X 16 STANDARD SRAM, 10 ns, PDSO44
封裝: 0.400 INCH, TSOP2-44
文件頁數(shù): 7/9頁
文件大?。?/td> 1397K
代理商: 71V416S10PHGI
6.42
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 (
CS
Controlled Timing)
(1,3)
7
NOTES:
1. A write occurs during the overlap of a LOW
CS
, LOW
BHE
or
BLE
, and a LOW
WE
.
2. During this period, I/O pins are in the output state, and input signals must not be applied.
3. If the
CS
LOW or
BHE
and
BLE
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
Timing Waveform of Write Cycle No. 3
(
BHE
,
BLE
Controlled Timing)
(1,3)
ADDRESS
CS
DATA
IN
3624 drw 09
DATA
IN
VALID
t
WC
t
AS
(2)
t
CW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
BHE, BLE
t
BW
t
WP
ADDRESS
CS
DATA
IN
3624 drw 10
DATA
IN
VALID
t
WC
t
AS
(2)
t
CW
t
WR
WE
AW
DATA
OUT
t
DW
t
DH
BHE, BLE
t
BW
t
WP
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