參數(shù)資料
型號: 71V3577YS75PF8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 128K X 36 CACHE SRAM, 7.5 ns, PQFP100
封裝: 14 X 20 MM, PLASTIC, TQFP-100
文件頁數(shù): 10/22頁
文件大小: 621K
代理商: 71V3577YS75PF8
6.42
18
IDT71V3577YS_79YS, IDT71V3577YSA_79YSA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
NOTES:
1. ZZ input is LOW,
ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles,
ADSP and ADSC function identically and are therefore interchangable.
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
GW, BWE, BWx
CE, CS1
CS0
ADDRESS
ADSC
DATAOUT
OE
Av
Aw
Ax
Ay
Az
(Av)
(Aw)
(Ax)
(Ay)
6450 drw 10
,
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
GW
CE, CS1
CS0
ADDRESS
ADSC
DATAIN
Av
Aw
Ax
Az
Ay
(Av)
(Aw)
(Ax)
(Az)
(Ay)
6450 drw 11
,
NOTES:
1. ZZ input is LOW,
ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only
GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles,
ADSP and ADSC have different limitations.
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