- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄158051 > 71V3557SA85BG8 (INTEGRATED DEVICE TECHNOLOGY INC) 128K X 36 ZBT SRAM, 8.5 ns, PBGA119 PDF資料下載
參數(shù)資料
| 型號(hào)： | 71V3557SA85BG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 ZBT SRAM, 8.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, POWER, PLASTIC, BGA-119 |
| 文件頁(yè)數(shù)： | 13/28頁(yè) |
| 文件大?。?/td> | 511K |
| 代理商： | 71V3557SA85BG8 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)當(dāng)前第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)
6.42
20
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation (1,2,3,4)
NOTES:
1.
Q
(A
1)
represents
the
first
output
from
the
external
address
A
1.
D
(A
2)
represents
the
input
data
to
the
SRAM
corresponding
to
address
A
2.
2.
C
E
2timing
transitions
are
identical
but
inverted
to
the
CE
1and
CE
2
signals.
For
example,
when
CE
1and
CE
2are
LOW
on
this
waveform,
CE
2is
HIGH.
3.
CEN
when
sampled
high
on
the
rising
edge
of
clock
will
block
that
L-H
transition
of
the
clock
from
propogating
into
the
SRAM.
The
part
will
behave
as
if
the
L-H
clock
transition
did
not
occur.
All
internal
registers
in
the
SRAM
will
retain
their
previous
state.
4.
Individual
Byte
Write
signals
(BW
x)
must
be
valid
on
all
write
and
burst-write
cycles.
A
write
cycle
is
initiated
when
R/
W
signal
is
sampled
LOW.
The
byte
write
information
comes
in
one
cycle
before
the
actual
data
is
presented
to
the
SRAM.
tH
E
tS
E
R
/W
A
1
A
2
C
LK
C
E
N
A
D
V
/LD
A
D
R
E
S
C
E
1
,
C
E
2
(2
)
B
W
1
-
B
W
4
O
E
D
A
T
A
O
U
T
Q
(A
1
)
tC
D
C
Q
(A
3
)
tC
D
tC
LZ
Q
(A
1
)
Q
(A
4
)
tC
D
tC
D
C
tC
H
Z
D
(A
2
)
tS
D
tH
D
tC
H
tC
L
tC
Y
C
tH
C
tS
C
A
4
A
5
tH
A
D
V
tS
A
D
V
tH
W
tS
W
tH
A
tS
A
3
tH
B
tS
B
D
A
T
A
IN
52
82
dr
w
09
B
(A
2
)
.
,
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 71V67703S75BQ | 256K X 36 CACHE SRAM, 7.5 ns, PBGA165 |
| 72-30-33 | 0 MHz - 4000 MHz RF/MICROWAVE FIXED ATTENUATOR |
| 72-40-43 | 0 MHz - 4000 MHz RF/MICROWAVE FIXED ATTENUATOR |
| 72-10-14 | 0 MHz - 4000 MHz RF/MICROWAVE FIXED ATTENUATOR |
| 72-30-13 | 0 MHz - 4000 MHz RF/MICROWAVE FIXED ATTENUATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 71V3558S100PFG | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 71V3558S100PFG8 | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 71V3558S100PFGI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 71V3558S100PFGI8 | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 71V3558S133BG | 制造商:Integrated Device Technology Inc 功能描述:4.5MBIT SRAM CHIP SYNC SINGLE 3.3V 256K X 18 4.2NS - Trays 制造商:Integrated Device Technology Inc 功能描述:IDT 71V3558S133BG, 4.5MBit SRAM Chip Sync Single 3.3V 256K x 18 4.2ns 119-Pin BGA |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。