參數(shù)資料
型號： 71V3557SA85BG8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 128K X 36 ZBT SRAM, 8.5 ns, PBGA119
封裝： 14 X 22 MM, POWER, PLASTIC, BGA-119
文件頁數(shù)： 10/28頁
文件大?。?/td> 511K
代理商： 71V3557SA85BG8
6.42
18
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles (1,2,3,4,5)
NOTES:
1.
D
(A
1)
represents
the
first
input
to
the
external
address
A
1.
D
(A
2)
represents
the
first
input
to
the
external
address
A
2;
D
(A
2+1
)represents
the
next
input
data
in
the
burst
sequence
of
the
base
address
A
2,
etc.
where
address
bits
A
0and
A
1are
advancing
for
the
four
word
burst
in
the
sequence
defined
by
the
state
of
the
LBO
input.
2.
C
E
2timing
transitions
are
identical
but
inverted
to
the
CE
1and
CE
2
signals.
For
example,
when
CE
1and
CE
2are
LOW
on
this
waveform,
CE
2is
HIGH.
3.
Burst
ends
when
new
address
and
control
are
loaded
into
the
SRAM
by
sampling
ADV/
LD
LOW.
4.
R
/W
is
don't
care
when
the
SRAM
is
bursting
(ADV/
LD
sampled
HIGH).
The
nature
of
the
burst
access
(Read
or
Write)
is
fixed
by
the
state
of
the
R/
W
signal
when
new
address
and
control
are
loaded
into
the
SRAM.
5.
Individual
Byte
Write
signals
(BW
x)
must
be
valid
on
all
write
and
burst-write
cycles.
A
write
cycle
is
initiated
when
R/
W
signal
is
sampled
LOW.
The
byte
write
information
comes
in
one
cycle
before
the
actual
data
is
presented
to
the
SRAM.
tH
E
tS
E
R
/W
A
1
A
2
C
LK
C
E
N
A
D
V
/LD
A
D
R
E
S
C
E
1
,
C
E
2
(2
)
B
W
1
-
B
W
4
O
E
D
A
T
A
IN
D
(A
1
)
D
(A
2
)
tH
D
tS
D
(C
E
N
hig
h
,
e
lim
in
a
te
s
c
u
rr
ent
L
-H
cl
o
c
k
ed
g
e
)
D
(A
2+
1
)
D
(A
2+
2
)
D
(A
2+
3
)
D
(A
2
)
B
ur
s
t
W
ri
te
W
ri
te
W
ri
te
(B
ur
s
t
W
ra
p
s
a
rou
nd
to
in
it
ial
s
ta
te
)
tH
D
tS
D
tC
H
tC
L
tC
Y
C
tH
A
D
V
tS
A
D
V
tH
W
tS
W
tH
A
tS
A
tH
C
tS
C
tH
B
tS
B
52
82
dr
w
07
B
(A
1
)
B
(A
2
)
B
(A
2+
1
)
B
(A
2+
2
)
B
(A
2+
3
)
B
(A
2
)
.
,
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