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參數(shù)資料
| 型號： | 71T016SA20BFGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 64K X 16 STANDARD SRAM, 20 ns, PBGA48 |
| 封裝： | 7 X 7 MM, PLASTIC, FBGA-48 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 477K |
| 代理商： | 71T016SA20BFGI |
6.42
7
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 (
CS
Controlled Timing)
(1,4)
NOTES:
1. A write occurs during the overlap of a LOW
CS
, LOW
BHE
or
BLE
, and a LOW
WE
.
2.
OE
is continuously HIGH. If during a
WE
controlled write cycle
OE
is LOW, t
WP
must be greater than or equal to t
WHZ
+ t
DW
to allow the I/O drivers to turn off and data to be placed
on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the mnimumwrite pulse is as short as the specified t
WP
.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the
CS
LOW or
BHE
and
BLE
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV fromsteady state.
Timing Waveform of Write Cycle No. 3 (
BHE
,
BLE
Controlled Timing)
(1,4)
ADDRESS
CS
DATA
IN
5326 drw 09
DATA
IN
VALID
t
WC
t
AS
(2)
t
CW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
BHE, BLE
t
BW
t
WP
ADDRESS
CS
DATA
IN
5326 drw 10
DATA
IN
VALID
t
WC
t
AS
(2)
t
CW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
BHE, BLE
t
BW
t
WP
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