參數(shù)資料
型號(hào): 70P249L65BYGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 4K X 16 DUAL-PORT SRAM, 40 ns, PBGA100
封裝: 0.50 MM PITCH, GREEN, BGA-100
文件頁(yè)數(shù): 16/22頁(yè)
文件大小: 146K
代理商: 70P249L65BYGI
6.42
3
IDT70P269/259/249L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
OCTOBER 16, 2008
Pin Names
Left Port
Right Port
Description
CSL
CSR
Chip Select (Input)
WEL
WER
Read/Write Enable (Input)
OEL
OER
Output Enable (Input)
A0L - A13L (1)
A0R - A13R (1)
Address (Input)
MSELL(2)
MSELR(2)
Mode Select (Input)
I/O0L - I/O15L
I/O0R - I/O15R
Address/Data (Input/Output)
ADVL(3)
ADVR (3)
Address Latch Enable (Input)
UBL
UBR
Upper Byte Enable (Input)
LBL
LBR
Lower Byte Enable (Input)
INTL
INTR
Interrupt Flag (Output)
BUSYL
BUSYR
Busy Flag (Output)
SFEN
Special Function Enable (Input)
IRR0 - IRR1(4)
Input Read Register (Inputs)
ODR0 - ODR4
Output Drive Register (Outputs)
VDD
Core Power Supply (Input)
VSS
Ground (Input)
VDDIOL
Left Port Power Supply (Input)
VDDIOR
Right Port Power Supply (Input)
7146 tbl 01
Truth Table I: ADM Interface Read/Write Control
Inputs
Outputs
Mode
ADV
CSWEOE
UB
LB
I/O0 - I/O15
X
H
X
High-Z
Deselected/Power Down
X
H
X
High-Z
Output Disable
X
H
High-Z
Upper and Lower Bytes Deselected
Pulse
L
H
LLL
DATAOUT (I/O0 - I/O15)
Read Upper and Lower Bytes
Pulse
L
H
L
H
L
DATAOUT (I/O0 - I/O7)
High-Z (I/O8 - I/O15)
Read Lower Byte Only
Pulse
L
H
L
H
High-Z (I/O0 - I/O7)
DATAOUT (I/O8 - I/O15)
Read Upper Byte Only
Pulse
L
X
L
DATAIN (I/O0 - I/O15)
Write Upper and Lower Bytes
Pulse
L
X
H
L
DATAIN (I/O0 - I/O7)
High-Z (I/O8 - I/O15)
Write Lower Byte Only
Pulse
L
X
L
H
High-Z (I/O0 - I/O7)
DATAIN (I/O8 - I/O15)
Write Upper Byte Only
7146 tb l 02a
1. A13 - A0 for IDT70P269; A12 - A0 for IDT70P259; A11 - A0 for IDT70P249.
2. MSEL = 0 for Standard SRAM operation, MSEL = 1 for Address/Data Mux
(ADM) operation.
3. ADV is only used when the port is in ADM mode.
4. IRR0 is A13L and IRR1 is A13R for 70P269.
NOTES:
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