VERSACLOCK LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR
參數(shù)資料
型號: 5P49EE602NLGI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 2/26頁
文件大?。?/td> 0K
描述: IC CLOCK GENERATOR 24QFN
標(biāo)準(zhǔn)包裝: 75
系列: VersaClock™
類型: 時鐘發(fā)生器
PLL: 帶旁路
輸入: LVTTL,晶體
輸出: LVCMOS,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 2:5
差分 - 輸入:輸出: 無/是
頻率 - 最大: 120MHz
除法器/乘法器: 是/無
電源電壓: 1.71 V ~ 1.89 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN(4x4)
包裝: 管件
其它名稱: 800-2525
IDT5P49EE602
VERSACLOCK LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
IDT VERSACLOCK LOW POWER CLOCK GENERATOR
10
IDT5P49EE602
REV L 072512
External I2C Interface Condition
EEPROM Interface
The IDT5P49EE602 can store its configuration in an internal
EEPROM. The contents of the device's internal
programming registers can be saved to the EEPROM by
issuing a save instruction (ProgSave) and can be loaded
back to the internal programming registers by issuing a
restore instruction (ProgRestore).
To initiate a save or restore using I2C, only two bytes are
transferred. The Device Address is issued with the
read/write bit set to “0”, followed by the appropriate
command code. The save or restore instruction executes
after the STOP condition is issued by the Master, during
which time the IDT5P49EE602 will not generate
Acknowledge bits. The IDT5P49EE602 will acknowledge
the instructions after it has completed execution of them.
During that time, the I2C bus should be interpreted as busy
by all other users of the bus.
On power-up of the IDT5P49EE602, an automatic restore is
performed to load the EEPROM contents into the internal
programming registers. The IDT5P49EE602 will be ready to
accept a programming instruction once it acknowledges its
7-bit I2C address.
Progwrite
Progwrite Command Frame
Writes can continue as long as a Stop condition is not sent and each byte will increment the register address.
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