參數(shù)資料
型號： 5962R0722402VYC
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256
封裝： QFP-256
文件頁數(shù)： 83/155頁
文件大?。?/td> 4139K
代理商： 5962R0722402VYC
AT697F PRELIMINARY INFORMATION
33
7703D–AERO–12/09
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
SDRAM
The synchronous dynamic RAM interface can manage up to two SDRAM banks. The control of
the SDRAM memory accesses uses a standard set of pin, including chip selects (SDCS*x), write
enable (SDWE*), data masks (SDDQM*x) and clock lines.
The bank size of the two SDRAM banks can be configured by setting the value of the
MCFG2
SDRBS. The bank size can be programmed in binary step from 4 Mbytes to 512
Mbytes.
The controller supports 64M, 256M and 512M devices with 8 to 12 column-address bits, up to 13
row-address bits, and 4 banks. Only 32-bit data bus width is supported for SDRAM banks.
Address Mapping
The start address for the SDRAM banks depends upon the SRAM use in the application. If the
the SRAM disable bit MCFG2 SI and the SDRAM enable bit MCFG2 SE are set logical one,
the SDRAM start address is 0x40000000. If the the SRAM disable bit MCFG2 SI is set logical
zero and the SDRAM enable bit MCFG2
SE is set logical one, the SDRAM start address is
0x60000000. If MCFG2 SE if set logical zero, no SDRAM can be used.
The address bus of the SDRAMs shall be connected to A[14:2], the bank address to A[16:15].
Devices with less than 13 address pins should only use the less significant bits of A[14:2].
Figure 17. SDRAM connection overview
AD
AT697F
A[27:0]
D[31:0]
RAS
CAS
WE
BA
D
SDRAM
SDRAS*
SDCAS*
SDWE*
A[16:15]
DQM
SDDQM[3:0]
CLK
CSN
SDCLK
SDCSN[1:0]
A
A[14:2]
SDRAM Timing
Parameters
To provide optimum access cycles for different SDRAM devices some SDRAM parameters can
be programmed through MCFG2 register. The programmable SDRAM parameters are the fol-
lowing :
Table 15. SDRAM Programmable Timing Parameters
Function
Parameter
Range
Unit
CAS latency
2 - 3
clocks
Precharge to activate
t
RP
2 - 3
clocks
Auto-refresh command period
t
RFC
3 - 11
clocks
Auto-refresh interval
10 - 32768
clocks
SDRAM Commands
The SDRAM controller can issue three SDRAM commands. Commands to be executed are pro-
grammed through the MCFG2
SDRCMD. When this field is writen with a non zero value, a
SDRAM command is issued :
if set to ‘01’, Precharge command is sent,
if set to ‘10’, Auto-Refresh command is sent,
if set to ‘11’, Load Mode Reg (LMR) is sent.
When the LMR command is issued, the MCFG2
SDRCAS delay programmed is used.
MCFG2 SDRCMD is cleared after a command is executed. When changing the value of the
CAS delay, a LOAD-MODE-REGISTER command should be generated at the same time.
The SDRAM controller also provides a refresh command. It can be enabled by setting a logical
one into MCFG2 SDRREF.
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