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參數資料
| 型號： | 5962R0722402VYC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256 |
| 封裝： | QFP-256 |
| 文件頁數： | 106/155頁 |
| 文件大?。?/td> | 4139K |
| 代理商： | 5962R0722402VYC |
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54
7703D–AERO–12/09
AT697F PRELIMINARY INFORMATION
PR
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IN
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3.
Enabling the interrupt signalisation is optionnal. It can be enabled setting logical one in
PCIITE IMIER. Up to four interrupt sources can be defined : Initiator Error, Initiator Par-
ity Error, PCI core error and system error.
4.
Engage an access to a memory address mapped in the PCI address range.
IO transaction cycles
operation
The following procedure shall be used to engage I/O transaction on the PCI interface:
1.
Select the initiator mode by setting logical one in PCIIC MOD.
2.
Select the I/O load/store command in the PCI initiator configuration register. The PCI-
IC COMMSB shall be set logical ‘00’ for I/O operation.
3.
Enabling the interrupt signalisation is optionnal. It can be enabled setting logical one in
PCIITE IMIER. Up to four interrupt sources can be defined : Initiator Error, Initiator Par-
ity Error, PCI core error and system error.
4.
Engage an access to an I/O address mapped in the PCI address range.
Configuration cycles
Target selection
Accesses to a configuration address space requires the target device to be selected. Due to the
address range limitation, the chip-select (IDSEL) connection necessary for device selection shall
be done using only A/D[27:16]. This allows up to 12 PCI devices to be connected on the bus.
Devices with chip-select line connected to A/D[31:28] can’t be configured through standard
operations. DMA configuration cycles shall be used to configure the devices connected to
A/D[31:28].
The PCI bus configuration cycles can be performed using the same instructions as the main
memory. To generate such configuration cycle with the standard instructions,PCIIC COMMS
shall be programmed to ‘01’.
Then, if a load (or store) cycle is performed to an addresss in the PCI address range, a physical
configuration cycle is performed on the PCI bus. The full 32-bit address defined on the internal
bus is propagated on the PCI bus. Once a target is selected (DEVSEL* asserted).
Operation
The following procedure shall be used to engage configuration cycle on the PCI interface:
1.
Select the initiator mode by setting logical one tin PCIIC MOD
2.
Select the configuration load/store command in PCIIC COMMS shall be set logical ‘10’
for configuration operation.
3.
Enabling the interrupt signalisation is optionnal. It can be enabled setting logical one in
PCIITE IMIER. Up to four interrupt sources can be defined : Initiator Error, Initiator Par-
ity Error, PCI core error and system error.
4.
Engage an access to an configuration space.
Limitation
Configuration cycles shall only be generated by the PCI host of the bus or by a PCI-to-PCI
bridges.
Special cycles
By default, all requests are translated into single cycle PCI transactions, each transaction con-
sisting in an address phase followed by a single data phase.
Linear incrementing
store-word
Linear incrementing store-word sequences are translated into undetermined length PCI write
bursts with up to a maximum of 255 words. The PCI burst mode is then maintained as long as
possible. Read/write direction is unchanged and the address An+1 = An + 4. When the sequence
is discontinued, the PCI burst stops with a last data phase during which byte enables are 1111.
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