參數(shù)資料
型號(hào): UPD44164362BF5-E40-EQ3-A
元件分類: SRAM
英文描述: 512K X 36 DDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
文件頁(yè)數(shù): 33/33頁(yè)
文件大?。?/td> 494K
代理商: UPD44164362BF5-E40-EQ3-A
μPD44164182B-A, μPD44164362B-A
R10DS0014EJ0100 Rev.1.00
Page 9 of 32
Dec 13, 2010
Burst Sequence
Linear Burst Sequence Table
A0
External Address
0
1
1st Internal Burst Address
1
0
Truth Table
Operation
LD# R, W#
CLK
DQ
WRITE cycle
L
→ H
Data in
Load address, input write data on
Input data
D(A1)
D(A2)
consecutive K and K# rising edge
Input clock
K(t+1)
K#(t+1)
READ cycle
L
H
L
→ H
Data out
Load address, read data on
Output data
Q(A1)
Q(A2)
consecutive C and C# rising edge
Output clock
C#(t+1)
C(t+2)
NOP (No operation)
H
×
L
→ H
High-Z
Clock stop
×
Stopped
Previous state
Remarks 1. H : HIGH, L : LOW,
× : don’t care, ↑ : rising edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges
except if C and C# are HIGH then Data outputs are delivered at K and K# rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
K. All control inputs are registered during the rising edge of K.
4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal burst
address in accordance with the linear burst sequence.
7. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most
rapid restart by overcoming transmission line charging symmetrically.
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