參數(shù)資料
型號(hào)： 28F320S5
英文描述： WORD-WIDE FlashFile MEMORY FAMILY
中文描述： 字寬FlashFile存儲(chǔ)器家族
文件頁(yè)數(shù)： 7/52頁(yè)
文件大?。?/td> 1262K
代理商： 28F320S5
E
28F160S3, 28F320S3
7
ADVANCE INFORMATION
Table 1. Pin Descriptions
Sym
Type
Name and Function
A
0
–A
21
INPUT
ADDRESS INPUTS:
Address inputs for read and write operations are internally
latched during a write cycle. A
0
selects high or low byte when operating in x8 mode.
In x16 mode, A
0
is not used; input buffer is off.
16-Mbit
→
A
0
–A
20
32-Mbit
→
A
0
–A
21
DATA INPUTS/OUTPUTS:
Inputs data and commands during CUI write cycles;
outputs data during memory array, Status Register, query and identifier code read
cycles. Data pins float to high-impedance when the chip is deselected or outputs
are disabled. Data is internally latched during a write cycle.
DQ
0
–
DQ
15
INPUT/
OUTPUT
CE
0
#,
CE
1
#
INPUT
CHIP ENABLE:
Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. With CE
0
# or CE
1
# high, the device is deselected and power
consumption reduces to standby levels. Both CE
0
# and CE
1
# must be low to select
the device. Device selection occurs with the latter falling edge of CE
0
# or CE
1
#. The
first rising edge of CE
0
# or CE
1
# disables the device.
RESET/DEEP POWER-DOWN:
When driven low, RP# inhibits write operations
which provides data protection during system power transitions, puts the device in
deep power-down mode, and resets internal automation. RP#-high enables normal
operation. Exit from deep power-down sets the device to read array mode.
RP#
INPUT
OE#
INPUT
OUTPUT ENABLE:
Gates the device’s outputs during a read cycle.
WE#
INPUT
WRITE ENABLE:
Controls writes to the CUI and array blocks. Addresses and data
are latched on the rising edge of the WE# pulse.
STS
OPEN
DRAIN
OUTPUT
STATUS:
Indicates the status of the internal state machine. When configured in
level mode (default), it acts as a RY/BY# pin. For this and alternate configurations
of the STATUS pin, see the Configuration command. Tie STS to V
CC
with a pull-up
resistor.
WP#
INPUT
WRITE PROTECT:
Master control for block locking. When V
IL
, locked blocks
cannot be erased or programmed, and block lock-bits cannot be set or cleared.
BYTE#
INPUT
BYTE ENABLE:
Configures x8 mode (low) or x16 mode (high).
V
PP
SUPPLY
BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY:
Necessary voltage to perform block erase, program, and lock-bit configuration
operations. Do not float any power pins.
V
CC
SUPPLY
DEVICE POWER SUPPLY:
Do not float any power pins. Do not attempt block
erase, program, or block-lock configuration with invalid V
CC
values.
SUPPLY
GROUND:
Do not float any ground pins.
GND
NC
NO CONNECT:
Lead is not internally connected; it may be driven or floated.
相關(guān)PDF資料
PDF描述
28F640J5 Dual-Slot, PCMCIA Analog Power Controller
28LV010RT2DB20 3.3V 1 Megabit (128K x 8-Bit) EEPROM
28LV010 3.3V 1 Megabit (128K x 8-Bit) EEPROM
28LV010RPDB20 3.3V 1 Megabit (128K x 8-Bit) EEPROM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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28F400B5 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SMART 5 BOOT BLOCK. FLASH MEMORY FAMILY 2. 4. 8 MBIT
28F400B5WG8BET 制造商: 功能描述: 制造商:Micron Technology Inc 功能描述: 制造商:undefined 功能描述:
28F400BL-B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-MBlT (256K x 16. 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY
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