參數(shù)資料
型號(hào)： 28F320S5
英文描述： WORD-WIDE FlashFile MEMORY FAMILY
中文描述： 字寬FlashFile存儲(chǔ)器家族
文件頁數(shù)： 6/52頁
文件大小： 1262K
代理商： 28F320S5
28F160S3, 28F320S3
E
6
ADVANCE INFORMATION
The device incorporates two Write Buffers of 32
bytes (16 words) to allow optimum-performance
data programming. This feature can improve
system program performance by up to four times
over non-buffer programming.
Individual block locking uses a combination of block
lock-bits to lock and unlock blocks. Block lock-bits
gate block erase, full chip erase, program and write
to
buffer
operations.
operations (Set Block Lock-Bit and Clear Block
Lock-Bits commands) set and clear lock-bits.
Lock-bit
configuration
The Status Register and the STS pin in RY/BY#
mode indicate whether or not the device is busy
executing an operation or ready for a new
command. Polling the Status Register, system
software retrieves WSM feedback. STS in RY/BY#
mode gives an additional indicator of WSM activity
by providing a hardware status signal. Like the
Status Register, RY/BY#-low indicates that the
WSM is performing a block erase, program, or lock-
bit operation. RY/BY#-high indicates that the WSM
is ready for a new command, block erase is
suspended (and program is inactive), program is
suspended, or the device is in deep power-down
mode.
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
The BYTE# pin allows either x8 or x16 read/writes
to the device. BYTE# at logic low selects 8-bit
mode with address A
selecting between the low
byte and high byte. BYTE# at logic high enables
16-bit operation with address A
becoming the
lowest order address. Address A
0
is not used in 16-
bit mode.
When one of the CE
X
# pins (CE
0
#, CE
1
#) and RP#
pins are at V
CC
, the component enters a CMOS
standby mode. Driving RP# to GND enables a deep
power-down mode which significantly reduces
power consumption, provides write protection,
resets the device, and clears the Status Register. A
reset time (t
PHQV
) is required from RP# switching
high until outputs are valid. Likewise, the device
has a wake time (t
PHEL
) from RP#-high until writes
to the CUI are recognized.
1.3
Pinout and Pin Description
The 16-Mbit device is available in the 56-lead
TSOP, 56-lead SSOP and
μ
BGA packages. The
32- Mb device is available in the 56-lead SSOP and
μBGA packages. The pinouts are shown in Figures
2, 3 and 4.
16-Mbit: Thirty-two
32-Mbit: Sixty-four
64-Kbyte Blocks
Input Buffer
O
M
Y-Gating
Program/Erase
Voltage Switch
Data
Comparator
Status
Register
Identifier
Register
D
R
I/O Logic
Address
Latch
Address
Counter
X-Decoder
Y-Decoder
Input Buffer
Output Buffer
GND
V
CC
BYTE#
V
PP
CE#
WE#
OE#
RP#
WP#
Command
User
Interface
16-Mbit: A
0
- A
20
32-Mbit: A
0 -
A
21
DQ
0
- DQ
15
V
CC
W
Write State
Machine
Multiplexer
Query
STS
Figure 1. Block Diagram
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