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參數(shù)資料
| 型號： | 28F320S3 |
| 英文描述： | WORD-WIDE FlashFile MEMORY FAMILY |
| 中文描述： | 字寬FlashFile存儲器家族 |
| 文件頁數(shù)： | 16/52頁 |
| 文件大?。?/td> | 1262K |
| 代理商： | 28F320S3 |
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28F160S3, 28F320S3
E
16
ADVANCE INFORMATION
NOTES:
1. Bus operations are defined in Table 2.
2. X = Any valid address within the device.
BA = Address within the block being erased or locked.
IA = Identifier Code Address: see Table 12.
QA = Query database Address.
PA = Address of memory location to be programmed.
3. ID = Data read from Query database.
SRD = Data read from Status Register. See Table 15 for a description of the Status Register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.
CC = Configuration Code. (See Table 14.)
4. The upper byte of the data bus (DQ
8
–15
) during command writes is a
“Don’t Care” in x16 operation.
5. Following the Read Identifier Codes command, read operations access manufacturer, device, and block-lock codes. See
Section 4.3 for read identifier code data.
6. If a block is locked (i.e., the block’s lock-bit is set to 0), WP# must be at V
in order to perform block erase, program and
suspend operations. Attempts to issue a block erase, program and suspend operation to a locked block while WP# is V
IL
will fail.
7. Either 40H or 10H are recognized by the WSM as the byte/word program setup.
8. After the Write to Buffer command is issued, check the XSR to make sure a Write Buffer is available.
9. N = byte/word count argument such that the number of bytes/words to be written to the input buffer = N + 1. N = 0 is 1
byte/word length, and so on. Write to Buffer is a multi-cycle operation, where a byte/word count of N + 1 is written to the
correct memory address (WA) with the proper data (WD). The Confirm command (D0h) is expected after exactly N + 1 write
cycles; any other command at that point in the sequence aborts the buffered write. Writing a byte/word count outside the
buffer boundary causes unexpected results and should be avoided.
10. The write to buffer, block erase, or full chip erase operation does not begin until a Confirm command (D0h) is issued.
Confirm also reactivates suspended operations.
11. A block lock-bit can be set only while WP# is V
IH
.
12. WP# must be at V
IH
to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits.
13. Commands other than those shown above are reserved for future use and should not be used.
14. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The
Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28F320S5 | WORD-WIDE FlashFile MEMORY FAMILY |
| 28F640J5 | Dual-Slot, PCMCIA Analog Power Controller |
| 28LV010RT2DB20 | 3.3V 1 Megabit (128K x 8-Bit) EEPROM |
| 28LV010 | 3.3V 1 Megabit (128K x 8-Bit) EEPROM |
| 28LV010RPDB20 | 3.3V 1 Megabit (128K x 8-Bit) EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F320S5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:WORD-WIDE FlashFile MEMORY FAMILY |
| 28F320W30 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| 28F400B3 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:SMART 3 ADVANCED BOOT BLOCK WORD-WIDE |
| 28F400B5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SMART 5 BOOT BLOCK. FLASH MEMORY FAMILY 2. 4. 8 MBIT |
| 28F400B5WG8BET | 制造商: 功能描述: 制造商:Micron Technology Inc 功能描述: 制造商:undefined 功能描述: |
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