參數(shù)資料
型號(hào): 28F320S3
英文描述: WORD-WIDE FlashFile MEMORY FAMILY
中文描述: 字寬FlashFile存儲(chǔ)器家族
文件頁數(shù): 10/52頁
文件大?。?/td> 1262K
代理商: 28F320S3
28F160S3, 28F320S3
E
10
ADVANCE INFORMATION
GND
A10
VPP
CE0
A14
VCC
A4
A7
A9
A11
A12
A15
A17
A19
A5
A6
A8
RP#
A13
A16
A21
A20
A2
A1
A3
A18
CE1
NC
NC
NC
BYTE#
DQ7
WP#
WE#
A0
DQ8
DQ1
DQ3
DQ12
DQ6
DQ15
OE#
DQ0
DQ9
DQ2
DQ11
DQ4
DQ13
DQ14
STS
VCC
DQ10
GND
VCC
DQ5
GND
GND A10
VPP CE0 A14
VCC
A4
A7
A9
A11
A12
A15
A17
A19
A5
A6
A8
RP# A13
A16
A21
A20
A2
A1
A3
A18
CE1 NC
NC
NC BYTE#
DQ7 WP# WE#
A0
DQ8 DQ1 DQ3 DQ12DQ6 DQ15OE#
DQ0 DQ9 DQ2 DQ11DQ4 DQ13DQ14STS
VCC DQ10GND VCC DQ5 GND
Bottom View
This is the view of the package as surface mounted on
the board. Note that the signals are mirror imaged.
NOTES:
1.
2.
3.
Figures are not drawn to scale.
Address A
21
is not included in the 28F160S3.
More information on μBGA* packages is available by contacting your Intel/Distribution sales office.
Figure 4.
μ
BGA* Package Pinout
2.0
PRINCIPLES OF OPERATION
The word-wide memories include an on-chip
Write State Machine (WSM) to manage block
erase, program,
and
functions. It allows for: 100% TTL-level control
inputs, fixed power supplies during block erasure,
programming, lock-bit configuration, and minimal
processor overhead with RAM-like interface
timings.
lock-bit
configuration
After initial device power-up or return from deep
power-down mode (see Bus Operations), the
device defaults to read array mode. Manipulation
of external memory control pins allow array read,
standby, and output disable operations.
Read Array, Status Register, query, and identifier
codes can be accessed through the CUI
independent
of
the
programming voltage on V
PP
enables successful
block
erasure,
program,
configuration. All functions associated with
altering memory contents
—block erase, program,
lock-bit configuration—are accessed via the CUI
and verified through the Status Register.
V
PP
voltage.
Proper
and
lock-bit
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