
28F160S3/28F320S3
E
10
PRELIMINARY
Interface software that initiates and polls
progress of block erase, programming, and lock-
bit configuration can be stored in any block. This
code is copied to and executed from system
RAM during flash memory updates. After
successful completion, reads are again possible
via the Read Array command. Block erase
suspend allows system software to suspend a
block erase to read or write data from any other
block. Program suspend allows system software
to suspend a program to read data from any
other flash memory array location.
2.1
Data Protection
Depending on the application, the system
designer may choose to make the V
PP
power
supply switchable or hardwired to V
PPH1/2/3
. The
device supports either design practice, and
encourages optimization of the processor-
memory interface.
When V
PP
≤
V
PPLK
, memory contents cannot be
altered. When high voltage is applied to V
PP
, the
two-step block erase, program, or lock-bit
configuration
command
protection from unwanted operations. All write
functions are disabled when V
CC
voltage is below
the write lockout voltage V
LKO
or when RP# is at
V
IL
. The device’s block locking capability
provides additional protection from inadvertent
code or data alteration.
sequences
provide
3.0
BUS OPERATION
The local CPU reads and writes flash memory in-
system. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
64-Kbyte Block
3FFFFF
3F0000
63
64-Kbyte Block
1FFFFF
1F0000
31
64-Kbyte Block
01FFFF
010000
00FFFF
000000
1
64-Kbyte Block
0
32-Kword Block
1FFFFF
1F0000
63
32-Kword Block
0FFFFF
0F8000
31
32-Kword Block
00FFFF
008000
007FFF
000000
1
32-Kword Block
0
32-Mbit: A[
21-1
]
16-Mbit: A[
20-1
]
32-Mbit: A[
21-0
]
16-Mbit: A[
20-0
]
Byte-Wide (x8) Mode
Word-Wide (x16) Mode
16 Mbit
32 Mbit
0608_05
Figure 4. Memory Map