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參數(shù)資料
| 型號： | 28233-11 |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM Transmitter/Receiver with UTOPIA Interface |
| 中文描述： | TRANSCEIVER, PQFP160 |
| 封裝： | PLASTIC, MQFP-160 |
| 文件頁數(shù)： | 62/161頁 |
| 文件大?。?/td> | 1832K |
| 代理商： | 28233-11 |
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cleared by the cell generation circuitry after the idle cell has been transmitted or if
a cell from another port is selected by the priority control. The microprocessor
can poll this bit to determine when the idle cell insertion has been completed.
Idle cells are automatically generated when no transmit port is active. The
header for idle cells is obtained from the TX_IDLE_xx registers, and the HEC is
automatically calculated. The payload for idle cells is obtained from the
IDLE_PAY register [0x2A]. This data octet is inserted in all octet positions of the
idle cell payload. The CRC-10 can be inserted if required by setting Disable
Payload CRC of CELL_GEN_x to zero.
2.0 Functional Description
CN8223
2.6 ATM Cell Processing
ATM Transmitter/Receiver with UTOPIA Interface
2-28
Conexant
100046C
Disable HEC [bit 9] and Disable Payload CRC [bit 10] in the CELL_GEN_x
registers [0x04
–
0x07], disable the field generation and allow the existing field to
pass. Error HEC [bit 11] and Error Payload CRC [bit 12] force a single error
occurrence in the generated field. The Error functions are cleared after the error
is generated. This allows the microprocessor to easily generate a specific number
of errors. The error pattern programmed in the TXFEAC_ERRPAT register
[0x03] is used with the Error HEC control to generate a specific number of HEC
errors for checking receiver error correction/detection circuitry.
The Error Payload CRC bit inserts 4-bit errors into the payload CRC field.
The Inhibit Single Cell Generation [bit 13] field in CELL_GEN_x, inhibits cell
transmission from the port for a single cell interval. A single idle cell (with header
contents as defined in the Transmit Idle Header Register [0x0A
–
0x0B] and
payload set to all 0s) is transmitted in place of a data cell from this port at the next
cell interval
if
the priority control tries to obtain a cell from this port. This bit is
2.6.1.2 Cell Generation
Status and Status
Interrupts for Transmit
A per-port count of cells transmitted is maintained in the CELL_SENT_CNTx
counters [0x4E
–
0x51] for each port. These counters can be programmed to cause
an interrupt in the CELL_STATUS register [0x3B] by setting enable bits in the
EN_CELL_INT register 0x30]. The interrupt clears when CELL_STATUS is
read. If the counter interrupt is not enabled, the counter stops at its maximum
value of 65,535. If the interrupt is enabled, the counter interrupts on
“
roll over
”
and continues counting. The counter clears when it is read.
Table 2-18. Overhead Field Locations
Overhead Field
Source
Cell Header
Header Register TX_HDR or FIFO input
Header Error Control
HEC Generation Circuit or FIFO input
Segment Type
FIFO Input
Sequence Count
FIFO Input
Length Field
FIFO Input
Payload CRC
Payload CRC Generation Circuit or FIFO Input
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